View ST92185B3T1_6245011.PDF datasheet online --- IC-ON-LINE

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october 2003 1/178 st92185b 16k/24k/32k rom hcmos mcu with on-screen-display n register file based 8/16 bit core architecture with run, wfi, slow and halt modes n 0c to +70c operating temperature range n up to 24 mhz. operation @ 5v10% n min. instruction cycle time: 165ns at 24 mhz. n 16, 24 or 32 kbytes rom n 256 bytes ram of register file (accumulators or index registers) n 256 bytes of on-chip static ram n 2 kbytes of tdsram (display storage ram) n 28 fully programmable i/o pins n serial peripheral interface n flexible clock controller for osd, data slicer and core clocks running from a single low frequency external crystal. n enhanced display controller with: C 26 rows of 40 characters or 24 rows of 80 characters C serial and parallel attributes C 10x10 dot matrix, 512 rom characters, defin- able by user C 4/3 and 16/9 supported in 50/60hz and 100/ 120 hz mode C rounding, fringe, double width, double height, scrolling, cursor, full background color, half- intensity color, translucency and half-tone modes n integrated sync extractor and sync controller n 14-bit voltage synthesis for tuning reference voltage n up to 6 external interrupts plus one non- maskable interrupt n 8 x 8-bit programmable pwm outputs with 5v open-drain or push-pull capability n 16-bit watchdog timer with 8-bit prescaler n one 16-bit standard timer with 8-bit prescaler n 4-channel a/d converter; 5-bit guaranteed n rich instruction set and 14 addressing modes n versatile development tools, including assembler, linker, c-compiler, archiver, source level debugger and hardware emulators with real-time operating system available from third parties n pin-compatible eprom and otp devices available (st92e195d7d1, st92t195d7b1) n pin-compatible with the st92195 family with embedded teletext decoder device summary device program memory tdsram vps/ wss st92185b1 16k rom 2k no st92185b2 24k rom 2k no st92185b3 32k rom 2k no psdip56 see end of datasheet for ordering information psdip42 tqfp64 1
2/178 table of contents 178 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . st92185b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 st9+ core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.2 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.3 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.4 tv peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.5 on screen display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.6 voltage synthesis tuning control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.7 pwm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.8 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.9 standard timer (stim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.10 analog/digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.1 i/o port alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.2.2 i/o port styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1 core architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2 memory spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.1 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.2 register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.1 central interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.2 flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 2.3.3 register pointing techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.4 paged registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.5 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.6 stack pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 2.4 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.5 memory management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6 address space extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6.1 addressing 16-kbyte pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6.2 addressing 64-kbyte segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.7 mmu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.7.1 dpr[3:0]: data page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.7.2 csr: code segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.7.3 isr: interrupt segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.7.4 dmasr: dma segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.8 mmu usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.8.1 normal program execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.8.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.8.3 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1
3/178 table of contents 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2 interrupt vectoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2.1 divide by zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2.2 segment paging during interrupt routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3 interrupt priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4 priority level arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4.1 priority level 7 (lowest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4.2 maximum depth of nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4.3 simultaneous interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4.4 dynamic priority level modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5 arbitration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5.1 concurrent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5.2 nested mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.6 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.7 top level interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.8 on-chip peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.9 interrupt response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.10 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4 reset and clock control unit (rccu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2 reset / stop manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.4 clock control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.5 reset control unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5 timing and clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1 frequency multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.2.1 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.2 specific port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3 port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.4 input/output bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.5 alternate function architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.5.1 pin declared as i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.5.2 pin declared as an alternate function input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.5.3 pin declared as an alternate function output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.6 i/o status after wfi, halt and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.1 timer/watchdog (wdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4/178 table of contents 178 7.1.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.1.3 watchdog timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.1.4 wdt interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.1.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.2 standard timer (stim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.2.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.2.3 interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.2.4 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.2.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.3 display storage ram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.3.3 initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.3.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.4 on screen display (osd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.4.2 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.4 programming the display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.4.5 vertical scrolling control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.4.6 display memory mapping examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.4.7 font mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 7.4.8 font mapping modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 7.4.9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.4.10 application software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.5 sync controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 7.5.1 h/v polarity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7.5.2 field detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7.5.3 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7.5.4 sync controller working modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7.5.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 7.6 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 7.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 42 7.6.2 device-specific options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 7.6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.6.4 interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.6.5 working with other protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.6.6 i2c-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.6.7 s-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 7.6.8 im-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 7.6.9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 7.7 a/d converter (a/d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 7.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 52 7.7.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5/178 table of contents 7.7.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 7.7.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.8 voltage synthesis tuning converter (vs) . . . . . . . . . . . . . . . . . . . . . . . . . . 156 7.8.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 56 7.8.2 output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 7.8.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 7.9 pwm generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 7.9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 61 7.9.2 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 9 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 72 9.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 9.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 9.2.1 transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6/178 st92185b - general description 1 general description 1.1 introduction the st92185b microcontroller is developed and manufactured by stmicroelectronics using a pro- prietary n-well hcmos process. its performance derives from the use of a flexible 256-register pro- gramming model for ultra-fast context switching and real-time event response. the intelligent on- chip peripherals offload the st9 core from i/o and data management processing tasks allowing criti- cal application tasks to get the maximum use of core resources. the st92185b mcu supports low power consumption and low voltage operation for power-efficient and low-cost embedded systems. 1.1.1 st9+ core the advanced core consists of the central processing unit (cpu), the register file and the interrupt controller. the general-purpose registers can be used as ac- cumulators, index registers, or address pointers. adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. although the st9 has an 8-bit alu, the chip handles 16-bit opera- tions, including arithmetic, loads/stores, and mem- ory/register and memory/memory exchanges. two basic addressable spaces are available: the memory space and the register file, which in- cludes the control and status registers of the on- chip peripherals. 1.1.2 power saving modes to optimize performance versus power consump- tion, a range of operating modes can be dynami- cally selected. run mode. this is the full speed execution mode with cpu and peripherals running at the maximum clock speed delivered by the phase locked loop (pll) of the clock control unit (ccu). wait for interrupt mode. the wait for interrupt (wfi) instruction suspends program execution un- til an interrupt request is acknowledged. during wfi, the cpu clock is halted while the peripheral and interrupt controller keep running at a frequen- cy programmable via the ccu. in this mode, the power consumption of the device can be reduced by more than 95% (low power wfi). halt mode. when executing the halt instruction, and if the watchdog is not enabled, the cpu and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). a reset is necessary to exit from halt mode. 1.1.3 i/o ports up to 28 i/o lines are dedicated to digital input/ output. these lines are grouped into up to five i/o ports and can be configured on a bit basis under software control to provide timing, status signals, timer and output, analog inputs, external interrupts and serial or parallel i/o. 1.1.4 tv peripherals a set of on-chip peripherals form a complete sys- tem for tv set and vcr applications: C voltage synthesis C display ram C osd 1.1.5 on screen display the human interface is provided by the on screen display module, this can produce up to 26 lines of up to 80 characters from a rom defined 512 char- acter set. the character resolution is 10x10 dot. four character sizes are supported. serial at- tributes allow the user to select foreground and background colors, character size and fringe back- ground. parallel attributes can be used to select additional foreground and background colors and underline on a character by character basis. note: the osd cell is common to all st92x195 family devices. however, its capabilities are limit- ed by a tdsram memory size of 2kbytes on the st92185 family. certain display modes using more than 2kbytes of memory are not available.
7/178 st92185b - general description introduction (contd) 1.1.6 voltage synthesis tuning control 14-bit voltage synthesis using the pwm (pulse width modulation)/brm (bit rate modulation) technique can be used to generate tuning voltages for tv set applications. the tuning voltage is out- put on one of two separate output pins. 1.1.7 pwm output control of tv settings can be made with up to eight 8-bit pwm outputs, with a maximum frequen- cy of 23,437hz at 8-bit resolution (intclk = 12 mhz). low resolutions with higher frequency oper- ation can be programmed. 1.1.8 serial peripheral interface (spi) the spi bus is used to communicate with external devices via the spi, or i2c bus communication standards. the spi uses a single data line for data input and output. a second line is used for a syn- chronous clock signal. 1.1.9 standard timer (stim) the st92185b has one standard timer (stim0) that includes a programmable 16-bit down counter and an associated 8-bit prescaler with single and continuous counting modes. 1.1.10 analog/digital converter (adc) in addition there is a 4-channel analog to digital converter with integral sample and hold, fast 5.75s conversion time and 6-bit guaranteed reso- lution.
8/178 st92185b - general description introduction (contd) figure 1. st92185b block diagram memory bus i/o port 0 register bus voltage synthesis pwm d/a con- verter spi i/o port 4 i/o port 5 24/32 kbytes rom 2 kbytes tdsram tri 256 bytes ram standard timer timing and clock ctrl 16-bit timer/ watchdog i/o port 2 adc i/o port 3 sync control vsync hsync/csync on screen display freq. multip. pxfm nmi int[7:4] int2 256 bytes register file st9+ core 8/16-bit cpu interrupt management rccu oscin oscout reset reseto p0[7:0] r/g/b/fb pwm[7:0] sdo/sdi sck int0 stout mmu mcfm tslu ain[4:1] vso[2:1] extrg p2[5:0] p4[7:0] p5[1:0] p3[7:4] cso ht all alternate functions (italic characters) are mapped on ports 0, 2, 3, 4 and 5 2 8 4 6 8
9/178 st92185b - general description 1.2 pin description reset reset (input, active low). the st9+ is ini- tialised by the reset signal. with the deactivation of reset, program execution begins from the program memory location pointed to by the vector contained in program memory locations 00h and 01h. r/g/b red/green/blue . video color analog dac outputs. fb fast blanking . video analog dac output. v dd main power supply voltage (5v 10%, digital) v pp : on eprom/otp devices, v pp is the pro- gramming voltage pin. v pp should be tied to gnd in user mode. mcfm analog pin for the display pixel frequency multiplier. oscin, oscout oscillator (input and output). these pins connect a parallel-resonant crystal (24mhz maximum), or an external source to the on-chip clock oscillator and buffer. oscin is the input of the oscillator inverter and internal clock generator; oscout is the output of the oscillator inverter. vsync vertical sync . vertical video synchronisa- tion input to osd. positive or negative polarity. hsync/csync horizontal/composite sync . hori- zontal or composite video synchronisation input to osd. positive or negative polarity. pxfm analog pin for the display pixel frequency multiplier avdd3 analog v dd of pll. this pin must be tied to v dd externally. gnd digital circuit ground. agnd analog circuit ground (must be tied exter- nally to digital gnd). avdd1, avdd2 analog power supplies (must be tied externally to v dd ). cvbso, jtdo, jtck, jtms test pins: leave floating. test0 test pin: must be tied to avdd2. jtrst0 test pin: must be tied to gnd. figure 2. 56-pin package pin-out int7/p2.0 reset p0.7 p0.6 p0.5 p0.4 p0.3 ain4/p0.2 p0.1 p0.0 cso/reset0 /p3.7 p3.6 p3.5 p3.4 b g r fb sdi/sdo/p5.1 sck/int2/p5.0 v dd jtdo n.c v pp avdd3 test0 mcfm jtck p2.1/int5/ain1 p2.2/int0/ain2 p2.3/int6/vs01 p2.4/nmi p2.5/ain3/int4/vs02 oscin oscout p4.7/pwm7/extrg/stout p4.6/pwm6 p4.5/pwm5 p4.4/pwm4 p4.3/pwm3/tslu/ht p4.2/pwm2 p4.1/pwm1 p4.0/pwm0 vsync hsync/csync avdd1 pxfm jtrsto gnd agnd n.c n.c jtms avdd2 cvbso n.c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
10/178 st92185b - general description pin description (contd) figure 3. st92185b required external components (56-pin package) +5v +5v p42 p 36 p 0 2 p 3 5 p22 p 5 1 p2 1 p 0 3 p 0 4 p 3 4 p4 1 p44 p 0 5 p 00 p4 7 p4 3 p 3 7 p 5 0 p 0 6 p24 p2 3 p 0 1 p2 0 p4 6 p2 5 p 0 7 p4 0 p4 5 c 1 3 4 . 7 nf c 1 0 4 . 7 nf c 3 3 9 p f c 1 3 9 p f r 2 5 . 6 k r 3 5 . 6 k c 11 22 p f c 2 1 f s 1 r s t d 1 1 n 4 1 4 8 c 8 22 p f c 6 1 00 nf c 4 1 0 f r 1 1 0 k l 2 1 0 uh y 1 4 mhz c 5 1 00 nf l 1 1 0 uh c 1 2 1 00 nf c 7 1 0 f c 9 1 00 nf u 1 s d i p 5 6 { 9 2 1 8 5 } 1 5 6 2 3 4 5 6 7 8 9 1 0 11 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 22 2 3 24 2 5 2 6 2 7 2 8 55 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 44 4 3 42 4 1 4 0 3 9 3 8 3 7 36 3 5 3 4 33 3 2 3 1 3 0 2 9 p2 . 0 / i n t 7 p2 . 1 / i n t 5 / a i n 1 r e s e t n p 0 . 7 p 0 . 6 p 0 . 5 p 0 . 4 p 0 . 3 p 0 . 2 / a i n 4 p 0 . 1 p 0 . 0 p 3 . 7 / r e s e t 0 / c s o p 3 . 6 p 3 . 5 p 3 . 4 b g r f b p 5 . 1 / s d i / s d o p 5 . 0 / s c k / i n t 2 v dd j t d o n . c n . c a v dd 3 t e s t 0 m c f m j t c k p2 . 2 / i n t 0 / a i n 2 p2 . 3 / i n t 6 / v s 0 1 p2 . 4 / n m i p2 . 5 / a i n 3 / i n t 4 / v s 0 2 o s c i n o s c o u t p4 . 7 / p w m 7 / e x t r g / s t o u t p4 . 6 / p w m 6 p4 . 5 / p w m 5 p4 . 4 / p w m 4 p4 . 3 / p w m 3 / t s l u p4 . 2 / p w m 2 p4 . 1 / p w m 1 p4 . 0 / p w m 0 v s y n c h s y n c / c s y n c a v dd 1 p x f m j t r s t o g n d a g n d n . c n . c j t m s a v dd 2 c v b s o n . c f b v s y n c r b h s y n c g
11/178 st92185b - general description pin description (contd) figure 4.. 42-pin package pin-out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 40 41 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 int7/p2.0 reset b p3.5 p3.6 cso/reset0 /p3.7 p0.0 p0.3 p0.4 p0.5 p0.6 p0.7 p0.1 ain4/p0.2 p3.4 sck/int2/p5.0 sdi/sdo/p5.1 r g fb v dd p2.1/int5/ain1 p2.2/int0/ain2 p4.0/pwm0 p4.2/pwm2 p4.3/pwm3/tslu/ht p4.4/pwm4 p4.5/pwm5 oscout oscin p2.5/ain3/int4/vs02 p2.4/nmi p2.3/int6/vs01 p4.6/pwm6 p4.7/pwm7/extrg/stout p4.1/pwm1 mcfm pxfm hsync/csync vsync test0 gnd
12/178 st92185b - general description figure 5. st92185b required external components (42-pin package) +5v p37 p 24 p3 5 p 01 p 2 3 p 0 2 p 22 p 4 6 p 4 3 p 4 1 p 4 0 p 5 0 p 0 3 p 4 7 p 0 6 p 0 5 p3 6 p 5 1 p 42 p 2 1 p 2 0 p 0 7 p 2 5 p 44 p3 4 p 0 4 p 00 p 4 5 c 3 3 9pf c 1 3 9pf c 2 1 f s 1 r s t d 1 1 n 4 1 4 8 c 6 100 n f c 4 10 f l 1 10 uh c 9 4 . 7 n f r 2 5 . 6 k c 8 22 pf r 3 5 . 6 k c 7 4 . 7 n f r 1 10 k y 1 4 mhz c 5 22 pf u 1 s d i p 42 { 9 2 1 8 5 } 1 42 2 3 4 5 6 7 8 9 10 11 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 4 1 4 0 3 9 3 8 37 3 6 3 5 3 4 33 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 24 2 3 22 2 1 p 2 . 0 / i n t 7p 2 . 1 / i n t 5 / a i n 1 r e s e t n p 0 . 7 p 0 . 6 p 0 . 5 p 0 . 4 p 0 . 3 p 0 . 2 / a i n 4 p 0 . 1 p 0 . 0 p3 . 7 / r e s e t 0 / c s o p3 . 6 p3 . 5 p3 . 4 b g r f b p 5 . 1 / s d i / s d o / i n t 1 p 5 . 0 / s c k / i n t 2 p 2 . 2 / i n t 0 / a i n 2 p 2 . 3 / i n t 6 / v s 01 p 2 . 4 / n m i p 2 . 5 / a i n 3 / i n t 4 / v s 0 2 o s c i n o s c o u t p 4 . 7 / p w m 7 / e x tr g / s t o u t p 4 . 6 / p w m 6 p 4 . 5 / p w m 5 p 4 . 4 / p w m 4 p 4 . 3 / p w m 3 / t s l u p 4 . 2 / p w m 2 p 4 . 1 / p w m 1 p 4 . 0 / p w m 0 v s y n c h s y n c t e s t 0 p x f m m c f m g n d v dd f b r b g v s y n c h s y n c
13/178 st92185b - general description figure 6. 64-pin package pin-out note: n.c = not connected gnd ain4/p0.2 p0.1 p0.0 cso/reset0 /p3.7 p3.6 p3.5 p3.4 b g r fb sdo/sdi/p5.1 int2/sck/p5.0 v dd jtdo v dd p0.3 p0.4 p0.5 p0.6 p0.7 reset p2.0/int7 p2.1/int5/ain1 p2.2/int0/ain2 p2.3/int6/vs01 p2.4/nmi p2.5/ain3/int4/vs02 oscin oscout v dd v ss p4.7/pwm7/extrg/stout p4.6/pwm6 p4.5/pwm5 p4.4/pwm4 p4.3/pwm3/tslu/ht p4.2/pwm2 p4.1/pwm1 p4.0/pwm0 vsync hsync/csync avdd1 pxfm jtrst0 gnd n.c. n.c. n.c. n.c v pp avdd3 test0 mcfm jtck n.c cvbso avdd2 jtms n.c n.c agnd n.c. 1 64 16 32 48 16
14/178 st92185b - general description pin description (contd) p0[7:0], p2[5:0], p3[7:4], p4[7:0], p5[1:0] i/o port lines (input/output, ttl or cmos com- patible). 28 lines grouped into i/o ports, bit programmable as general purpose i/o or as alternate functions (see i/o section). important : note that open-drain outputs are for logic levels only and are not true open drain. 1.2.1 i/o port alternate functions. each pin of the i/o ports of the st92185b may as- sume software programmable alternate functions (see table 1). table 1. st92185b i/o port alternate function summary port name general purpose i/o pin no. alternate functions sdip42 sdip56 p0.0 all ports useable for general pur- pose i/o (input, output or bidi- rectional) 10 10 i/o p0.1 9 9 i/o p0.2 8 8 ain4 i a/d analog data input 4 p0.3 7 7 i/o p0.4 6 6 i/o p0.5 5 5 i/o p0.6 4 4 i/o p0.7 3 3 i/o p2.0 1 1 int7 i external interrupt 7 p2.1 42 56 ain1 i a/d analog data input 1 int5 i external interrupt 5 p2.2 41 55 int0 i external interrupt 0 ain2 i a/d analog data input 2 p2.3 40 54 int6 i external interrupt 6 vso1 o voltage synthesis output 1 p2.4 39 53 nmi i non maskable interrupt input p2.5 38 52 ain3 i a/d analog data input 3 int4 i external interrupt 4 vso2 o voltage synthesis output 2 p3.4 14 14 i/o p3.5 13 13 i/o p3.6 12 12 i/o p3.7 11 11 reset0 o internal reset output cso o composite sync output p4.0 28 42 pwm0 o pwm output 0 p4.1 29 43 pwm1 o pwm output 1 p4.2 30 44 pwm2 o pwm output 2 p4.3 31 45 pwm3 o pwm output 3 tslu o translucency digital output ht o half-tone output p4.4 32 46 pwm4 o pwm output 4
15/178 st92185b - general description p4.5 all ports useable for general pur- pose i/o (input, output or bidi- rectional) 33 47 pwm5 o pwm output 5 p4.6 34 48 pwm6 o pwm output 6 p4.7 35 49 extrg i a/d converter external trigger input pwm7 o pwm output 7 stout o standard timer output p5.0 20 20 int2 i external interrupt 2 sck o spi serial clock p5.1 19 19 sdo o spi serial data out sdi i spi serial data in port name general purpose i/o pin no. alternate functions sdip42 sdip56
16/178 st92185b - general description pin description (contd) 1.2.2 i/o port styles legend: af= alternate function, bid = bidirectional, od = open drain pp = push-pull, ttl = ttl standard input levels how to read this table to configure the i/o ports, use the information in this table and the port bit configuration table in the i/o ports chapter on page 69 . port style = the hardware characteristics fixed for each port line. inputs: C if port style = standard i/o, either ttl or cmos input level can be selected by software. C if port style = schmitt trigger, selecting cmos or ttl input by software has no effect, the input will always be schmitt trigger. weak pull-up = this column indicates if a weak pull-up is present or not. C if wpu = yes, then the wpu can be enabled/dis- able by software C if wpu = no, then enabling the wpu by software has no effect alternate functions (af) = more than one af cannot be assigned to an external pin at the same time: an alternate function can be selected as follows. af inputs: C af is selected implicitly by enabling the corre- sponding peripheral. exception to this are adc analog inputs which must be explicitly selected as af by software. af outputs or bidirectional lines: C in the case of outputs or i/os, af is selected explicitly by software. example 1: adc trigger digital input af: extrg, port: p4.7, port style: standard i/o. write the port configuration bits (for ttl level): p4c2.7=1 p4c1.7=0 p4c0.7=1 enable the adc trigger by software as described in the adc chapter. example 2: pwm 0 output af: pwm0, port: p4.0 write the port configuration bits (for output push- pull): p4c2.0=0 p4c1.0=1 p4c0.0=1 example 3: adc analog input af: ain1, port : p2.1, port style: does not apply to analog inputs write the port configuration bits: p2c2.1=1 p2c1.1=1 p2c0.1=1 pins weak pull-up port style reset values p0[7:0] no standard i/o bid / od / ttl p2[5,4,3,2] no standard i/o bid / od / ttl p2[1,0] no schmitt trigger bid / od / ttl p3.7 yes standard i/o af / pp / ttl p3[6,5,4] no standard i/o bid / od / ttl p4[7:0] no standard i/o bid / od / ttl p5[1:0] no standard i/o bid / od / ttl
17/178 st92185b - general description 1.3 memory map internal rom the rom memory is mapped in a single continu- ous area starting at address 0000h in mmu seg- ment 00h. internal ram, 256 bytes the internal ram is mapped in mmu segment 20h; from address ff00h to ffffh. internal tdsram the internal tdsram is mapped starting at ad- dress 8000h in mmu segment 22h. it is a fully stat- ic memory. figure 7. st92185b memory map device size start address end address st92185b1 16k 0000h 3fffh st92185b2 24k 0000h 5fffh st92185b3 32k 0000h 7fffh device size start address end address st92185b1/b2/b3 2k 8000h 87ffh segment 0 64 kbytes 00ffffh 00c000h 00bfffh 008000h 007fffh 004000h 000000h 003fffh page 0 - 16 kbytes page 1 - 16 kbytes page 2 - 16 kbytes page 3 - 16 kbytes segment 20h 64 kbytes 200000h 21ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80 - 16 kbytes page 81 - 16 kbytes page 82 - 16 kbytes page 83 - 16 kbytes 20ff00h 20ffffh ram 256 bytes internal reserved segment 21h 64 kbytes 20ffffh 220000h 22ffffh 210000h segment 22h 64 kbytes 228000h 2287ffh 2kbytes tdsram internal rom page 88 - 16 kbytes page 89 - 16 kbytes page 90 - 16 kbytes page 91 - 16 kbytes 22c000h 22bfffh 228000h 227fffh 224000h 223fffh reserved reserved reserved reserved reserved reserved max. 64 kbytes 32 kbytes internal rom 000000h 007fffh 005fffh 24k bytes internal rom 16k bytes 24 kbytes 003fffh
18/178 st92185b - general description 1.4 register map the following pages contain a list of st92185b registers, grouped by peripheral or function. be very careful to correctly program both: C the set of registers dedicated to a particular function or peripheral. C registers common to other functions. in particular, double-check that any registers with undefined reset values have been correctly ini- tialised. warning : note that in the eivr and each ivr reg- ister, all bits are significant. take care when defin- ing base vector addresses that entries in the inter- rupt vector table do not overlap. group f pages register map register page 0 2 311213233353839555962 r255 res. res. res. res. res. osd tsu res res. rccu (pll) vs res. r254 spi port 3 tcc r253 res. r252 wcr mmu tdsram pwm r251 wdt res. res r250 port 2 res. res. r249 r248 r247 ext int res. res. res. r246 port 5 mmu r245 r244 r243 res. stim sync r242 port 0 port 4 a/d r241 res. res. r240
19/178 st92185b - general description table 2. detailed register map group f page dec. block reg. no. register name description reset value hex. doc. page n/a i/o port 0:5 r224 p0dr port 0 data register ff 66 r226 p2dr port 2 data register ff r227 p3dr port 3 data register ff r228 p4dr port 4 data register ff r229 p5dr port 5 data register ff core r230 cicr central interrupt control register 87 53 r231 flagr flag register 00 26 r232 rp0 pointer 0 register xx 28 r233 rp1 pointer 1 register xx 28 r234 ppr page pointer register xx 30 r235 moder mode register e0 30 r236 usphr user stack pointer high register xx 33 r237 usplr user stack pointer low register xx 33 r238 ssphr system stack pointer high reg. xx 33 r239 ssplr system stack pointer low reg. xx 33 0 int r242 eitr external interrupt trigger register 00 53 r243 eipr external interrupt pending reg. 00 54 r244 eimr external interrupt mask-bit reg. 00 54 r245 eiplr external interrupt priority level reg. ff 54 r246 eivr external interrupt vector register x6 55 r247 nicr nested interrupt control 00 55 wdt r248 wdthr watchdog timer high register ff 78 r249 wdtlr watchdog timer low register ff 78 r250 wdtpr watchdog timer prescaler reg. ff 78 r251 wdtcr watchdog timer control register 12 78 r252 wcr wait control register 7f 79 spi r253 spidr spi data register xx 150 r254 spicr spi control register 00 150 2 i/o port 0 r240 p0c0 port 0 configuration register 0 00 66 r241 p0c1 port 0 configuration register 1 00 r242 p0c2 port 0 configuration register 2 00 i/o port 2 r248 p2c0 port 2 configuration register 0 00 r249 p2c1 port 2 configuration register 1 00 r250 p2c2 port 2 configuration register 2 00 i/o port 3 r252 p3c0 port 3 configuration register 0 00 r253 p3c1 port 3 configuration register 1 00 r254 p3c2 port 3 configuration register 2 00
20/178 st92185b - general description 3 i/o port 4 r240 p4c0 port 4 configuration register 0 00 66 r241 p4c1 port 4 configuration register 1 00 r242 p4c2 port 4 configuration register 2 00 i/o port 5 r244 p5c0 port 5 configuration register 0 00 r245 p5c1 port 5 configuration register 1 00 r246 p5c2 port 5 configuration register 2 00 11 stim r240 sth counter high byte register ff 83 r241 stl counter low byte register ff 83 r242 stp standard timer prescaler register ff 83 r243 stc standard timer control register 14 83 21 mmu r240 dpr0 data page register 0 xx 38 r241 dpr1 data page register 1 xx 38 r242 dpr2 data page register 2 xx 38 r243 dpr3 data page register 3 xx 38 r244 csr code segment register 00 39 r248 isr interrupt segment register xx 39 r249 dmasr dma segment register xx 39 ext.mem. r246 emr2 external memory register 2 0f 56 32 osd r240 hblankr horizontal blank register 03 121 r241 hposr horizontal position register 03 121 r242 vposr vertical position register 00 121 r243 fsccr full screen color control register 00 122 r244 hscr header & status control register 2a 123 r245 ncsr national character set control register 00 124 r246 chposr cursor horizontal position register 00 125 r247 cvposr cursor vertical position register 00 125 r248 sclr scrolling control low register 00 126 r249 schr scrolling control high register 00 127 r250 dcm0r display control mode 0 register 00 129 r251 dcm1r display control mode 1 register 00 130 r252 tdpr tdsram pointer register 00 130 r253 de0r display enable 0 control register ff 131 r254 de1r display enable 1 control register ff 131 r255 de2r display enable 2 control register xf 131 33 r240 dcr default color register 70 132 r241 capvr cursor absolute vertical position register 00 132 r246 tdppr tdsram page pointer register x0 132 r247 tdhspr tdsram header/status pointer register x0 132 35 sync r242 sccs0r sync controller control and status register 0 00 140 r243 sccs1r sync controller control and status register 1 00 141 38 tdsram r252 config tdsram interface configuration register 02 87 group f page dec. block reg. no. register name description reset value hex. doc. page
21/178 st92185b - general description note: xx denotes a byte with an undefined value, however some of the bits may have defined values. refer to register description for details. 39 tcc r251 pxccr pll clock control register 00 66 r252 slccr slicer clock control register 00 66 r253 mccr main clock control register 00 65 r254 skccr skew clock control register 00 65 55 rccu r251 pconf pll configuration register 07 61 r254 sdrath clock slow down unit ratio register 2x,4x or 00 61 59 pwm r240 cm0 compare register 0 00 163 r241 cm1 compare register 1 00 163 r242 cm2 compare register 2 00 163 r243 cm3 compare register 3 00 163 r244 cm4 compare register 4 00 163 r245 cm5 compare register 5 00 163 r246 cm6 compare register 6 00 163 r247 cm7 compare register 7 00 163 r248 acr autoclear register ff 164 r249 ccr counter register 00 164 r250 pctl prescaler and control register 0c 164 r251 ocpl output complement register 00 165 r252 oer output enable register 00 165 vs r254 vsdr1 data and control register 1 00 160 r255 vsdr2 data register 2 00 160 62 adc r240 addtr channel i data register xx 155 r241 adclr control logic register 00 154 r242 adint ad interrupt register 01 155 group f page dec. block reg. no. register name description reset value hex. doc. page
22/178 st92185b - device architecture 2 device architecture 2.1 core architecture the st9 core or central processing unit (cpu) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as bcd and boolean formats; 14 address- ing modes are available. four independent buses are controlled by the core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit in- terrupt/dma bus which connects the interrupt and dma controllers in the on-chip peripherals with the core. this multiple bus architecture affords a high de- gree of pipelining and parallel operation, thus mak- ing the st9 family devices highly efficient, both for numerical calculation, data handling and with re- gard to communication with on-chip peripheral re- sources. 2.2 memory spaces there are two separate memory spaces: C the register file, which comprises 240 8-bit registers, arranged as 15 groups (group 0 to e), each containing sixteen 8-bit registers plus up to 64 pages of 16 registers mapped in group f, which hold data and control bits for the on-chip peripherals and i/os. C a single linear memory space accommodating both program and data. all of the physically sep- arate memory areas, including the internal rom, internal ram and external memory are mapped in this common address space. the total ad- dressable memory space of 4 mbytes (limited by the size of on-chip memory and the number of external address pins) is arranged as 64 seg- ments of 64 kbytes. each segment is further subdivided into four pages of 16 kbytes, as illus- trated in figure 1 . a memory management unit uses a set of pointer registers to address a 22-bit memory field using 16-bit address-based instruc- tions. 2.2.1 register file the register file consists of (see figure 2 ): C 224 general purpose registers (group 0 to d, registers r0 to r223) C 6 system registers in the system group (group e, registers r224 to r239) C up to 64 pages, depending on device configura- tion, each containing up to 16 registers, mapped to group f (r240 to r255), see figure 3 . figure 8. single program and data memory address space 3fffffh 3f0000h 3effffh 3e0000h 20ffffh 02ffffh 020000h 01ffffh 010000h 00ffffh 000000h 8 7 6 5 4 3 2 1 0 63 62 2 1 0 address 16k pages 64k segments up to 4 mbytes data code 255 254 253 252 251 250 249 248 247 9 10 11 21ffffh 210000h 133 134 135 33 reserved 132
23/178 st92185b - device architecture memory spaces (contd) figure 9. register groups figure 10. page pointer for group f mapping figure 11. addressing the register file f e d c b a 9 8 7 6 5 4 3 paged registers system registers 2 1 0 00 15 255 240 239 224 223 va00432 up to 64 pages general registers purpose 224 page 63 page 5 page 0 page pointer r255 r240 r224 r0 va00433 r234 register file system registers group d group b group c (1100) (0011) r192 r207 255 240 239 224 223 f e d c b a 9 8 7 6 5 4 3 2 1 0 15 vr000118 00 r195 r195 (r0c3h) paged registers
24/178 st92185b - device architecture memory spaces (contd) 2.2.2 register addressing register file registers, including group f paged registers (but excluding group d), may be ad- dressed explicitly by means of a decimal, hexa- decimal or binary address; thus r231, re7h and r11100111b represent the same register (see figure 4 ). group d registers can only be ad- dressed in working register mode. note that an upper case r is used to denote this direct addressing mode. working registers certain types of instruction require that registers be specified in the form rx , where x is in the range 0 to 15: these are known as working regis- ters. note that a lower case r is used to denote this in- direct addressing mode. two addressing schemes are available: a single group of 16 working registers, or two separately mapped groups, each consisting of 8 working reg- isters. these groups may be mapped starting at any 8 or 16 byte boundary in the register file by means of dedicated pointer registers. this tech- nique is described in more detail in section 1.3.3 , and illustrated in figure 5 and in figure 6 . system registers the 16 registers in group e (r224 to r239) are system registers and may be addressed using any of the register addressing modes. these registers are described in greater detail in section 1.3 . paged registers up to 64 pages, each containing 16 registers, may be mapped to group f. these are addressed us- ing any register addressing mode, in conjunction with the page pointer register, r234, which is one of the system registers. this register selects the page to be mapped to group f and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. therefore if the page pointer, r234, is set to 5, the instructions: spp #5 ld r242, r4 will load the contents of working register r4 into the third register of page 5 (r242). these paged registers hold data and control infor- mation relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between st9 devices. the number of these regis- ters therefore depends on the peripherals which are present in the specific st9 family device. in other words, pages only exist if the relevant pe- ripheral is present. table 3. register file organization hex. address decimal address function register file group f0-ff 240-255 paged registers group f e0-ef 224-239 system registers group e d0-df 208-223 general purpose registers group d c0-cf 192-207 group c b0-bf 176-191 group b a0-af 160-175 group a 90-9f 144-159 group 9 80-8f 128-143 group 8 70-7f 112-127 group 7 60-6f 96-111 group 6 50-5f 80-95 group 5 40-4f 64-79 group 4 30-3f 48-63 group 3 20-2f 32-47 group 2 10-1f 16-31 group 1 00-0f 00-15 group 0
25/178 st92185b - device architecture 2.3 system registers the system registers are listed in table 2 system registers (group e) . they are used to perform all the important system settings. their purpose is de- scribed in the following pages. refer to the chapter dealing with i/o for a description of the port[5:0] data registers. table 4. system registers (group e) 2.3.1 central interrupt control register please refer to the interrupt chapter for a de- tailed description of the st9 interrupt philosophy. central interrupt control register (cicr) r230 - read/write register group: e (system) reset value: 1000 0111 (87h) bit 7 = gcen : global counter enable . this bit is the global counter enable of the multi- function timers. the gcen bit is anded with the ce bit in the tcr register (only in devices featur- ing the mft multifunction timer) in order to enable the timers when both bits are set. this bit is set af- ter the reset cycle. note: if an mft is not included in the st9 device, then this bit has no effect. bit 6 = tlip : top level interrupt pending . this bit is set by hardware when a top level inter- rupt request is recognized. this bit can also be set by software to simulate a top level interrupt request. 0: no top level interrupt pending 1: top level interrupt pending bit 5 = tli : top level interrupt bit . 0: top level interrupt is acknowledged depending on the tlnm bit in the nicr register. 1: top level interrupt is acknowledged depending on the ien and tlnm bits in the nicr register (described in the interrupt chapter). bit 4 = ien : interrupt enable . this bit is cleared by interrupt acknowledgement, and set by interrupt return ( iret ). ien is modified implicitly by iret , ei and di instructions or by an interrupt acknowledge cycle. it can also be explic- itly written by the user, but only when no interrupt is pending. therefore, the user should execute a di instruction (or guarantee by other means that no interrupt request can arrive) before any write operation to the cicr register. 0: disable all interrupts except top level interrupt. 1: enable interrupts bit 3 = iam : interrupt arbitration mode . this bit is set and cleared by software to select the arbitration mode. 0: concurrent mode 1: nested mode. bits 2:0 = cpl[2:0] : current priority level . these three bits record the priority level of the rou- tine currently running (i.e. the current priority lev- el, cpl). the highest priority level is represented by 000, and the lowest by 111. the cpl bits can be set by hardware or software and provide the reference according to which subsequent inter- rupts are either left pending or are allowed to inter- rupt the current interrupt service routine. when the current interrupt is replaced by one of a higher pri- ority, the current priority value is automatically stored until required in the nicr register. r239 (efh) ssplr r238 (eeh) ssphr r237 (edh) usplr r236 (ech) usphr r235 (ebh) mode register r234 (eah) page pointer register r233 (e9h) register pointer 1 r232 (e8h) register pointer 0 r231 (e7h) flag register r230 (e6h) central int. cntl reg r229 (e5h) port5 data reg. r228 (e4h) port4 data reg. r227 (e3h) port3 data reg. r226 (e2h) port2 data reg. r225 (e1h) port1 data reg. r224 (e0h) port0 data reg. 70 gcen tlip tli ien iam cpl2 cpl1 cpl0
26/178 st92185b - device architecture system registers (contd) 2.3.2 flag register the flag register contains 8 flags which indicate the cpu status. during an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the end of the interrupt service rou- tine, thus returning the cpu to its original status. this occurs for all interrupts and, when operating in nested mode, up to seven versions of the flag register may be stored. flag register (flagr) r231- read/write register group: e (system) reset value: 0000 0000 (00h ) bit 7 = c : carry flag . the carry flag is affected by: addition ( add, addw, adc, adcw ), subtraction ( sub, subw, sbc, sbcw ), compare ( cp, cpw ), shift right arithmetic ( sra, sraw ), shift left arithmetic ( sla, slaw ), swap nibbles ( swap ), rotate ( rrc, rrcw, rlc, rlcw, ror, rol ), decimal adjust ( da ), multiply and divide ( mul, div, divws ). when set, it generally indicates a carry out of the most significant bit position of the register being used as an accumulator (bit 7 for byte operations and bit 15 for word operations). the carry flag can be set by the set carry flag ( scf ) instruction, cleared by the reset carry flag ( rcf ) instruction, and complemented by the com- plement carry flag ( ccf ) instruction. bit 6 = z: zero flag . the zero flag is affected by: addition ( add, addw, adc, adcw ), subtraction ( sub, subw, sbc, sbcw ), compare ( cp, cpw ), shift right arithmetic ( sra, sraw ), shift left arithmetic ( sla, slaw ), swap nibbles ( swap ), rotate (rrc , rrcw, rlc, rlcw, ror, rol) , decimal adjust ( da ), multiply and divide ( mul, div, divws ), logical ( and, andw, or, orw, xor, xorw, cpl ), increment and decrement ( inc, incw, dec, decw ), test ( tm, tmw, tcm, tcmw, btset ). in most cases, the zero flag is set when the contents of the register being used as an accumulator be- come zero, following one of the above operations. bit 5 = s : sign flag . the sign flag is affected by the same instructions as the zero flag. the sign flag is set when bit 7 (for a byte opera- tion) or bit 15 (for a word operation) of the register used as an accumulator is one. bit 4 = v : overflow flag . the overflow flag is affected by the same instruc- tions as the zero and sign flags. when set, the overflow flag indicates that a two's- complement number, in a result register, is in er- ror, since it has exceeded the largest (or is less than the smallest), number that can be represent- ed in twos-complement notation. bit 3 = da : decimal adjust flag . the da flag is used for bcd arithmetic. since the algorithm for correcting bcd operations is differ- ent for addition and subtraction, this flag is used to specify which type of instruction was executed last, so that the subsequent decimal adjust ( da ) operation can perform its function correctly. the da flag cannot normally be used as a test condi- tion by the programmer. bit 2 = h : half carry flag. the h flag indicates a carry out of (or a borrow in- to) bit 3, as the result of adding or subtracting two 8-bit bytes, each representing two bcd digits. the h flag is used by the decimal adjust ( da ) instruc- tion to convert the binary result of a previous addi- tion or subtraction into the correct bcd result. like the da flag, this flag is not normally accessed by the user. bit 1 = reserved bit (must be 0). bit 0 = dp : data/program memory flag . this bit indicates the memory area addressed. its value is affected by the set data memory ( sdm ) and set program memory ( spm ) instructions. re- fer to the memory management unit for further de- tails. 70 c z s v da h - dp
27/178 st92185b - device architecture system registers (contd) if the bit is set, data is accessed using the data pointers (dprs registers), otherwise it is pointed to by the code pointer (csr register); therefore, the user initialization routine must include a sdm instruction. note that code is always pointed to by the code pointer (csr). note: in the current st9 devices, the dp flag is only for compatibility with software developed for the first generation of st9 devices. with the single memory addressing space, its use is now redun- dant. it must be kept to 1 with a sdm instruction at the beginning of the program to ensure a normal use of the different memory pointers. 2.3.3 register pointing techniques two registers within the system register group, are used as pointers to the working registers. reg- ister pointer 0 (r232) may be used on its own as a single pointer to a 16-register working space, or in conjunction with register pointer 1 (r233), to point to two separate 8-register spaces. for the purpose of register pointing, the 16 register groups of the register file are subdivided into 32 8- register blocks. the values specified with the set register pointer instructions refer to the blocks to be pointed to in twin 8-register mode, or to the low- er 8-register block location in single 16-register mode. the set register pointer instructions srp , srp0 and srp1 automatically inform the cpu whether the register file is to operate in single 16-register mode or in twin 8-register mode. the srp instruc- tion selects the single 16-register group mode and specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatical- ly select the twin 8-register group mode and spec- ify the locations of each 8-register block. there is no limitation on the order or position of these register groups, other than that they must start on an 8-register boundary in twin 8-register mode, or on a 16-register boundary in single 16- register mode. the block number should always be an even number in single 16-register mode. the 16-regis- ter group will always start at the block whose number is the nearest even number equal to or lower than the block number specified in the srp instruction. avoid using odd block numbers, since this can be confusing if twin mode is subsequently selected. thus: srp #3 will be interpreted as srp #2 and will al- low using r16 ..r31 as r0 .. r15. in single 16-register mode, the working registers are referred to as r0 to r15 . in twin 8-register mode, registers r0 to r7 are in the block pointed to by rp0 (by means of the srp0 instruction), while registers r8 to r15 are in the block pointed to by rp1 (by means of the srp1 instruction). caution : group d registers can only be accessed as working registers using the register pointers, or by means of the stack pointers. they cannot be addressed explicitly in the form rxxx .
28/178 st92185b - device architecture system registers (contd) pointer 0 register (rp0) r232 - read/write register group: e (system) reset value: xxxx xx00 (xxh) bits 7:3 = rg[4:0] : register group number. these bits contain the number (in the range 0 to 31) of the register block specified in the srp0 or srp instructions. in single 16-register mode the number indicates the lower of the two 8-register blocks to which the 16 working registers are to be mapped, while in twin 8-register mode it indicates the 8-register block to which r0 to r7 are to be mapped. bit 2 = rps : register pointer selector . this bit is set by the instructions srp0 and srp1 to indicate that the twin register pointing mode is se- lected. the bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: single register pointing mode 1: twin register pointing mode bits 1:0: reserved. forced by hardware to zero. pointer 1 register (rp1) r233 - read/write register group: e (system) reset value: xxxx xx00 (xxh) this register is only used in the twin register point- ing mode. when using the single register pointing mode, or when using only one of the twin register groups, the rp1 register must be considered as reserved and may not be used as a general purpose register. bits 7:3 = rg[4:0]: register group number. these bits contain the number (in the range 0 to 31) of the 8-register block specified in the srp1 in- struction, to which r8 to r15 are to be mapped. bit 2 = rps : register pointer selector . this bit is set by the srp0 and srp1 instructions to indicate that the twin register pointing mode is se- lected. the bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: single register pointing mode 1: twin register pointing mode bits 1:0: reserved. forced by hardware to zero. 70 rg4 rg3 rg2 rg1 rg0 rps 0 0 70 rg4 rg3 rg2 rg1 rg0 rps 0 0
29/178 st92185b - device architecture system registers (contd) figure 12. pointing to a single group of 16 registers figure 13. pointing to two groups of 8 registers 31 30 29 28 27 26 25 9 8 7 6 5 4 3 2 1 0 f e d 4 3 2 1 0 block number register group register file register pointer 0 srp #2 set by: instruction points to: group 1 addressed by block 2 r15 r0 31 30 29 28 27 26 25 9 8 7 6 5 4 3 2 1 0 f e d 4 3 2 1 0 block number register group register file register pointer 0 srp0 #2 set by: instructions point to: group 1 addressed by block 2 & register pointer 1 srp1 #7 & group 3 addressed by block 7 r7 r0 r15 r8
30/178 st92185b - device architecture system registers (contd) 2.3.4 paged registers up to 64 pages, each containing 16 registers, may be mapped to group f. these paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between st9 devices. the number of these registers depends on the pe- ripherals present in the specific st9 device. in oth- er words, pages only exist if the relevant peripher- al is present. the paged registers are addressed using the nor- mal register addressing modes, in conjunction with the page pointer register, r234, which is one of the system registers. this register selects the page to be mapped to group f and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. thus the instructions: spp #5 ld r242, r4 will load the contents of working register r4 into the third register of page 5 (r242). warning: during an interrupt, the ppr register is not saved automatically in the stack. if needed, it should be saved/restored by the user within the in- terrupt routine. page pointer register (ppr) r234 - read/write register group: e (system) reset value: xxxx xx00 (xxh ) bits 7:2 = pp[5:0] : page pointer . these bits contain the number (in the range 0 to 63) of the page specified in the spp instruction. once the page pointer has been set, there is no need to refresh it unless a different page is re- quired. bits 1:0: reserved. forced by hardware to 0. 2.3.5 mode register the mode register allows control of the following operating parameters: C selection of internal or external system and user stack areas, C management of the clock frequency, C enabling of bus request and wait signals when interfacing to external memory. mode register (moder) r235 - read/write register group: e (system) reset value: 1110 0000 (e0h) bit 7 = ssp : system stack pointer . this bit selects an internal or external system stack area. 0: external system stack area, in memory space. 1: internal system stack area, in the register file (reset state). bit 6 = usp : user stack pointer . this bit selects an internal or external user stack area. 0: external user stack area, in memory space. 1: internal user stack area, in the register file (re- set state). bit 5 = div2 : crystal oscillator clock divided by 2 . this bit controls the divide-by-2 circuit operating on the crystal oscillator clock (clock1). 0: clock divided by 1 1: clock divided by 2 70 pp5 pp4 pp3 pp2 pp1 pp0 0 0 70 ssp usp div2 prs2 prs1 prs0 brqen himp
31/178 st92185b - device architecture bits 4:2 = prs[2:0] : cpuclk prescaler . these bits load the prescaler division factor for the internal clock (intclk). the prescaler factor se- lects the internal clock frequency, which can be di- vided by a factor from 1 to 8. refer to the reset and clock control chapter for further information. bit 1 = brqen : bus request enable . 0: external memory bus request disabled 1: external memory bus request enabled on breq pin (where available). note: disregard this bit if breq pin is not availa- ble. bit 0 = himp : high impedance enable . when any of ports 0, 1, 2 or 6 depending on de- vice configuration, are programmed as address and data lines to interface external memory, these lines and the memory interface control lines (as, ds, r/w) can be forced into the high impedance
32/178 st92185b - device architecture system registers (contd) state by setting the himp bit. when this bit is reset, it has no effect. setting the himp bit is recommended for noise re- duction when only internal memory is used. if port 1 and/or 2 are declared as an address and as an i/o port (for example: p10... p14 = address, and p15... p17 = i/o), the himp bit has no effect on the i/o lines. 2.3.6 stack pointers two separate, double-register stack pointers are available: the system stack pointer and the user stack pointer, both of which can address registers or memory. the stack pointers point to the bottom of the stacks which are f illed using the push commands and emptied using the pop commands. the stack pointer is automatically pre-decremented when data is pushed in and post-incremented when data is popped out. the push and pop commands used to manage the system stack may be addressed to the user stack by adding the suffix u . to use a stack in- struction for a word, the suffix w is added. these suffixes may be combined. when bytes (or words) are popped out from a stack, the contents of the stack locations are un- changed until fresh data is loaded. thus, when data is popped from a stack area, the stack con- tents remain unchanged. note: instructions such as: pushuw rr236 or pushw rr238, as well as the corresponding pop instructions (where r236 & r237, and r238 & r239 are themselves the user and system stack pointers respectively), must not be used, since the pointer values are themselves automatically changed by the push or pop instruction, thus cor- rupting their value. system stack the system stack is used for the temporary stor- age of system and/or control data, such as the flag register and the program counter. the following automatically push data onto the system stack: C interrupts when entering an interrupt, the pc and the flag register are pushed onto the system stack. if the encsr bit in the emr2 register is set, then the code segment register is also pushed onto the system stack. C subroutine calls when a call instruction is executed, only the pc is pushed onto stack, whereas when a calls in- struction (call segment) is executed, both the pc and the code segment register are pushed onto the system stack. C link instruction the link or linku instructions create a c lan- guage stack frame of user-defined length in the system or user stack. all of the above conditions are associated with their counterparts, such as return instructions, which pop the stored data items off the stack. user stack the user stack provides a totally user-controlled stacking area. the user stack pointer consists of two registers, r236 and r237, which are both used for address- ing a stack in memory. when stacking in the reg- ister file, the user stack pointer high register, r236, becomes redundant but must be consid- ered as reserved. stack pointers both system and user stacks are pointed to by double-byte stack pointers. stacks may be set up in ram or in the register file. only the lower byte will be required if the stack is in the register file. the upper byte must then be considered as re- served and must not be used as a general purpose register. the stack pointer registers are located in the sys- tem group of the register file, this is illustrated in table 2 system registers (group e) . stack location care is necessary when managing stacks as there is no limit to stack sizes apart from the bottom of any address space in which the stack is placed. consequently programmers are advised to use a stack pointer value as high as possible, particular- ly when using the register file as a stacking area. group d is a good location for a stack in the reg- ister file, since it is the highest available area. the stacks may be located anywhere in the first 14 groups of the register file (internal stacks) or in ram (external stacks). note . stacks must not be located in the paged register group or in the system register group.
33/178 st92185b - device architecture system registers (contd) user stack pointer high register (usphr) r236 - read/write register group: e (system) reset value: undefined user stack pointer low register (usplr) r237 - read/write register group: e (system) reset value: undefined figure 14. internal stack mode system stack pointer high register (ssphr) r238 - read/write register group: e (system) reset value: undefined system stack pointer low register (ssplr) r239 - read/write register group: e (system) reset value: undefined figure 15. external stack mode 70 usp15 usp14 usp13 usp12 usp11 usp10 usp9 usp8 70 usp7 usp6 usp5 usp4 usp3 usp2 usp1 usp0 f e d 4 3 2 1 0 register file stack pointer (low) points to: stack 70 ssp15 ssp14 ssp13 ssp12 ssp11 ssp10 ssp9 ssp8 70 ssp7 ssp6 ssp5 ssp4 ssp3 ssp2 ssp1 ssp0 f e d 4 3 2 1 0 register file stack pointer (low) point to: stack memory stack pointer (high) &
34/178 st92185b - device architecture 2.4 memory organization code and data are accessed within the same line- ar address space. all of the physically separate memory areas, including the internal rom, inter- nal ram and external memory are mapped in a common address space. the st9 provides a total addressable memory space of 4 mbytes. this address space is ar- ranged as 64 segments of 64 kbytes; each seg- ment is again subdivided into four 16 kbyte pages. the mapping of the various memory areas (inter- nal ram or rom, external memory) differs from device to device. each 64-kbyte physical memory segment is mapped either internally or externally; if the memory is internal and smaller than 64 kbytes, the remaining locations in the 64-kbyte segment are not used (reserved). refer to the register and memory map chapter for more details on the memory map.
35/178 st92185b - device architecture 2.5 memory management unit the cpu core includes a memory management unit (mmu) which must be programmed to per- form memory accesses (even if external memory is not used). the mmu is controlled by 7 registers and 2 bits (encsr and dprrem) present in emr2, which may be written and read by the user program. these registers are mapped within group f, page 21 of the register file. the 7 registers may be sub-divided into 2 main groups: a first group of four 8-bit registers (dpr[3:0]), and a second group of three 6-bit registers (csr, isr, and dmasr). the first group is used to extend the address during data memory access (dpr[3:0]). the second is used to manage program and data memory ac- cesses during code execution (csr), interrupts service routines (isr or csr), and dma trans- fers (dmasr or isr). figure 16. page 21 registers dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 r255 r254 r253 r252 r251 r250 r249 r248 r247 r246 r245 r244 r243 r242 r241 r240 ffh feh fdh fch fbh fah f9h f8h f7h f6h f5h f4h f3h f2h f1h f0h mmu em page 21 mmu mmu bit dprrem=0 ssplr ssphr usplr usphr moder ppr rp1 rp0 flagr cicr p5dr p4dr p3dr p2dr p1dr p0dr dmasr isr emr2 emr1 csr dpr3 dpr2 1 dpr0 bit dprrem=1 ssplr ssphr usplr usphr moder ppr rp1 rp0 flagr cicr p5dr p4dr p3dr p2dr p1dr p0dr dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 relocation of p[3:0] and dpr[3:0] registers (default setting)
36/178 st92185b - device architecture 2.6 address space extension to manage 4 mbytes of addressing space, it is necessary to have 22 address bits. the mmu adds 6 bits to the usual 16-bit address, thus trans- lating a 16-bit virtual address into a 22-bit physical address. there are 2 different ways to do this de- pending on the memory involved and on the oper- ation being performed. 2.6.1 addressing 16-kbyte pages this extension mode is implicitly used to address data memory space if no dma is being performed. the data memory space is divided into 4 pages of 16 kbytes. each one of the four 8-bit registers (dpr[3:0], data page registers) selects a differ- ent 16-kbyte page. the dpr registers allow ac- cess to the entire memory space which contains 256 pages of 16 kbytes. data paging is performed by extending the 14 lsb of the 16-bit address with the contents of a dpr register. the two msbs of the 16-bit address are interpreted as the identification number of the dpr register to be used. therefore, the dpr registers are involved in the following virtual address rang- es: dpr0: from 0000h to 3fffh; dpr1: from 4000h to 7fffh; dpr2: from 8000h to bfffh; dpr3: from c000h to ffffh. the contents of the selected dpr register specify one of the 256 possible data memory pages. this 8-bit data page number, in addition to the remain- ing 14-bit page offset address forms the physical 22-bit address (see figure 10 ). a dpr register cannot be modified via an address- ing mode that uses the same dpr register. for in- stance, the instruction popw dpr0 is legal only if the stack is kept either in the register file or in a memory location above 8000h, where dpr2 and dpr3 are used. otherwise, since dpr0 and dpr1 are modified by the instruction, unpredicta- ble behaviour could result. figure 17. addressing via dpr[3:0] dpr0 dpr1 dpr2 dpr3 00 01 10 11 16-bit virtual address 22-bit physical address 8 bits mmu registers 2 m sb 14 lsb
37/178 st92185b - device architecture address space extension (contd) 2.6.2 addressing 64-kbyte segments this extension mode is used to address data memory space during a dma and program mem- ory space during any code execution (normal code and interrupt routines). three registers are used: csr, isr, and dmasr. the 6-bit contents of one of the registers csr, isr, or dmasr define one out of 64 memory seg- ments of 64 kbytes within the 4 mbytes address space. the register contents represent the 6 msbs of the memory address, whereas the 16 lsbs of the address (intra-segment address) are given by the virtual 16-bit address (see figure 11 ). 2.7 mmu registers the mmu uses 7 registers mapped into group f, page 21 of the register file and 2 bits of the emr2 register. most of these registers do not have a default value after reset. 2.7.1 dpr[3:0]: data page registers the dpr[3:0] registers allow access to the entire 4 mbyte memory space composed of 256 pages of 16 kbytes. 2.7.1.1 data page register relocation if these registers are to be used frequently, they may be relocated in register group e, by program- ming bit 5 of the emr2-r246 register in page 21. if this bit is set, the dpr[3:0] registers are located at r224-227 in place of the port 0-3 data registers, which are re-mapped to the default dpr's loca- tions: r240-243 page 21. data page register relocation is illustrated in fig- ure 9 . figure 18. addressing via csr, isr, and dmasr fetching program data memory fetching interrupt instruction accessed in dma instruction or dma access to program memory 16-bit virtual address 22-bit physical address 6 bits mmu registers csr isr dmasr 1 2 3 1 2 3
38/178 st92185b - device architecture mmu registers (contd) data page register 0 (dpr0) r240 - read/write register page: 21 reset value: undefined this register is relocated to r224 if emr2.5 is set. bits 7:0 = dpr0_[7:0] : these bits define the 16- kbyte data memory page number. they are used as the most significant address bits (a21-14) to ex- tend the address during a data memory access. the dpr0 register is used when addressing the virtual address range 0000h-3fffh. data page register 1 (dpr1) r241 - read/write register page: 21 reset value: undefined this register is relocated to r225 if emr2.5 is set. bits 7:0 = dpr1_[7:0] : these bits define the 16- kbyte data memory page number. they are used as the most significant address bits (a21-14) to ex- tend the address during a data memory access. the dpr1 register is used when addressing the virtual address range 4000h-7fffh. data page register 2 (dpr2) r242 - read/write register page: 21 reset value: undefined this register is relocated to r226 if emr2.5 is set. bits 7:0 = dpr2_[7:0] : these bits define the 16- kbyte data memory page. they are used as the most significant address bits (a21-14) to extend the address during a data memory access. the dpr2 register is involved when the virtual address is in the range 8000h-bfffh. data page register 3 (dpr3) r243 - read/write register page: 21 reset value: undefined this register is relocated to r227 if emr2.5 is set. bits 7:0 = dpr3_[7:0] : these bits define the 16- kbyte data memory page. they are used as the most significant address bits (a21-14) to extend the address during a data memory access. the dpr3 register is involved when the virtual address is in the range c000h-ffffh. 70 dpr0_7 dpr0_6 dpr0_5 dpr0_4 dpr0_3 dpr0_2 dpr0_1 dpr0_0 70 dpr1_7 dpr1_6 dpr1_5 dpr1_4 dpr1_3 dpr1_2 dpr1_1 dpr1_0 70 dpr2_7 dpr2_6 dpr2_5 dpr2_4 dpr2_3 dpr2_2 dpr2_1 dpr2_0 70 dpr3_7 dpr3_6 dpr3_5 dpr3_4 dpr3_3 dpr3_2 dpr3_1 dpr3_0
39/178 st92185b - device architecture mmu registers (contd) 2.7.2 csr: code segment register this register selects the 64-kbyte code segment being used at run-time to access instructions. it can also be used to access data if the spm instruc- tion has been executed (or ldpp, ldpd, lddp ). only the 6 lsbs of the csr register are imple- mented, and bits 6 and 7 are reserved. the csr register allows access to the entire memory space, divided into 64 segments of 64 kbytes. to generate the 22-bit program memory address, the contents of the csr register is directly used as the 6 msbs, and the 16-bit virtual address as the 16 lsbs. note: the csr register should only be read and not written for data operations (there are some ex- ceptions which are documented in the following paragraph). it is, however, modified either directly by means of the jps and calls instructions, or indirectly via the stack, by means of the rets in- struction. code segment register (csr) r244 - read/write register page: 21 reset value: 0000 0000 (00h) bits 7:6 = reserved, keep in reset state. bits 5:0 = csr_[5:0] : these bits define the 64- kbyte memory segment (among 64) which con- tains the code being executed. these bits are used as the most significant address bits (a21-16). 2.7.3 isr: interrupt segment register interrupt segment register (isr) r248 - read/write register page: 21 reset value: undefined isr and encsr bit (emr2 register) are also de- scribed in the chapter relating to interrupts, please refer to this description for further details. bits 7:6 = reserved, keep in reset state. bits 5:0 = isr_[5:0] : these bits define the 64- kbyte memory segment (among 64) which con- tains the interrupt vector table and the code for in- terrupt service routines and dma transfers (when the ps bit of the dapr register is reset). these bits are used as the most significant address bits (a21-16). the isr is used to extend the address space in two cases: C whenever an interrupt occurs: isr points to the 64-kbyte memory segment containing the inter- rupt vector table and the interrupt service routine code. see also the interrupts chapter. C during dma transactions between the peripheral and memory when the ps bit of the dapr regis- ter is reset : isr points to the 64 k-byte memory segment that will be involved in the dma trans- action. 2.7.4 dmasr: dma segment register dma segment register (dmasr) r249 - read/write register page: 21 reset value: undefined bits 7:6 = reserved, keep in reset state. bits 5:0 = dmasr_[5:0] : these bits define the 64- kbyte memory segment (among 64) used when a dma transaction is performed between the periph- eral's data register and memory, with the ps bit of the dapr register set. these bits are used as the most significant address bits (a21-16). if the ps bit is reset, the isr register is used to extend the ad- dress. 70 00 csr_5 csr_4 csr_3 csr_2 csr_1 csr_0 70 0 0 isr_5 isr_4 isr_3 isr_2 isr_1 isr_0 70 00 dma sr_5 dma sr_4 dma sr_3 dma sr_2 dma sr_1 dma sr_0
40/178 st92185b - device architecture mmu registers (contd) figure 19. memory addressing scheme (example) 3fffffh 294000h 240000h 23ffffh 20c000h 200000h 1fffffh 040000h 03ffffh 030000h 020000h 010000h 00c000h 000000h dmasr isr csr dpr3 dpr2 dpr1 dpr0 4m bytes 16k 16k 16k 64k 64k 64k 16k
41/178 st92185b - device architecture 2.8 mmu usage 2.8.1 normal program execution program memory is organized as a set of 64- kbyte segments. the program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps , calls and rets instructions, which automatically modify the csr, must be used to jump across segment boundaries. writing to the csr is forbidden during normal program execution because it is not syn- chronized with the opcode fetch. this could result in fetching the first byte of an instruction from one memory segment and the second byte from anoth- er. writing to the csr is allowed when it is not be- ing used, i.e during an interrupt service routine if encsr is reset. note that a routine must always be called in the same way, i.e. either always with call or always with calls , depending on whether the routine ends with ret or rets . this means that if the rou- tine is written without prior knowledge of the loca- tion of other routines which call it, and all the pro- gram code does not fit into a single 64-kbyte seg- ment, then calls / rets should be used. in typical microcontroller applications, less than 64 kbytes of ram are used, so the four data space pages are normally sufficient, and no change of dpr[3:0] is needed during program execution. it may be useful however to map part of the rom into the data space if it contains strings, tables, bit maps, etc. if there is to be frequent use of paging, the user can set bit 5 (dprrem) in register r246 (emr2) of page 21. this swaps the location of registers dpr[3:0] with that of the data registers of ports 0- 3. in this way, dpr registers can be accessed without the need to save/set/restore the page pointer register. port registers are therefore moved to page 21. applications that require a lot of paging typically use more than 64 kbytes of exter- nal memory, and as ports 0, 1 and 2 are required to address it, their data registers are unused. 2.8.2 interrupts the isr register has been created so that the in- terrupt routines may be found by means of the same vector table even after a segment jump/call. when an interrupt occurs, the cpu behaves in one of 2 ways, depending on the value of the enc- sr bit in the emr2 register (r246 on page 21). if this bit is reset (default condition), the cpu works in original st9 compatibility mode. for the duration of the interrupt service routine, the isr is used instead of the csr, and the interrupt stack frame is kept exactly as in the original st9 (only the pc and flags are pushed). this avoids the need to save the csr on the stack in the case of an interrupt, ensuring a fast interrupt response time. the drawback is that it is not possible for an interrupt service routine to perform segment calls / jps : these instructions would update the csr, which, in this case, is not used (isr is used instead). the code size of all interrupt service rou- tines is thus limited to 64 kbytes. if, instead, bit 6 of the emr2 register is set, the isr is used only to point to the interrupt vector ta- ble and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and the flags, and then the csr is loaded with the isr. in this case, an iret will also restore the csr from the stack. this approach lets interrupt service routines access the whole 4-mbyte address space. the drawback is that the interrupt response time is slightly increased, because of the need to also save the csr on the stack. compatibility with the original st9 is also lost in this case, because the interrupt stack frame is different; this difference, however, would not be noticeable for a vast major- ity of programs. data memory mapping is independent of the value of bit 6 of the emr2 register, and remains the same as for normal code execution: the stack is the same as that used by the main program, as in the st9. if the interrupt service routine needs to access additional data memory, it must save one (or more) of the dprs, load it with the needed memory page and restore it before completion. 2.8.3 dma depending on the ps bit in the dapr register (see dma chapter) dma uses either the isr or the dmasr for memory accesses: this guarantees that a dma will always find its memory seg- ment(s), no matter what segment changes the ap- plication has performed. unlike interrupts, dma transactions cannot save/restore paging registers, so a dedicated segment register (dmasr) has been created. having only one register of this kind means that all dma accesses should be pro- grammed in one of the two following segments: the one pointed to by the isr (when the ps bit of the dapr register is reset), and the one refer- enced by the dmasr (when the ps bit is set).
42/178 st92185b - interrupts 3 interrupts 3.1 introduction the st9 responds to peripheral and external events through its interrupt channels. current pro- gram execution can be suspended to allow the st9 to execute a specific response routine when such an event occurs, providing that interrupts have been enabled, and according to a priority mechanism. if an event generates a valid interrupt request, the current program status is saved and control passes to the appropriate interrupt service routine. the st9 cpu can receive requests from the fol- lowing sources: C on-chip peripherals C external pins C top-level pseudo-non-maskable interrupt according to the on-chip peripheral features, an event occurrence can generate an interrupt re- quest which depends on the selected mode. up to eight external interrupt channels, with pro- grammable input trigger edge, are available. in ad- dition, a dedicated interrupt channel, set to the top-level priority, can be devoted either to the ex- ternal nmi pin (where available) to provide a non- maskable interrupt, or to the timer/watchdog. in- terrupt service routines are addressed through a vector table mapped in memory. figure 20. interrupt response n 3.2 interrupt vectoring the st9 implements an interrupt vectoring struc- ture which allows the on-chip peripheral to identify the location of the first instruction of the interrupt service routine automatically. when an interrupt request is acknowledged, the peripheral interrupt module provides, through its interrupt vector register (ivr), a vector to point into the vector table of locations containing the start addresses of the interrupt service routines (defined by the programmer). each peripheral has a specific ivr mapped within its register file pages. the interrupt vector table, containing the address- es of the interrupt service routines, is located in the first 256 locations of memory pointed to by the isr register, thus allowing 8-bit vector addressing. for a description of the isr register refer to the chapter describing the mmu. the user power on reset vector is stored in the first two physical bytes in memory, 000000h and 000001h. the top level interrupt vector is located at ad- dresses 0004h and 0005h in the segment pointed to by the interrupt segment register (isr). with one interrupt vector register, it is possible to address several interrupt service routines; in fact, peripherals can share the same interrupt vector register among several interrupt channels. the most significant bits of the vector are user pro- grammable to define the base vector address with- in the vector table, the least significant bits are controlled by the interrupt module, in hardware, to select the appropriate vector. note : the first 256 locations of the memory seg- ment pointed to by isr can contain program code. 3.2.1 divide by zero trap the divide by zero trap vector is located at ad- dresses 0002h and 0003h of each code segment; it should be noted that for each code segment a divide by zero service routine is required. warning . although the divide by zero trap oper- ates as an interrupt, the flag register is not pushed onto the system stack automatically. as a result it must be regarded as a subroutine, and the service routine must end with the ret instruction (not iret ). normal program flow interrupt service routine iret instruction interrupt vr001833 clear pending bit
43/178 st92185b - interrupts interrupt vectoring (contd) 3.2.2 segment paging during interrupt routines the encsr bit in the emr2 register can be used to select between original st9 backward compati- bility mode and st9+ interrupt management mode. st9 backward compatibility mode (encsr = 0) if encsr is reset, the cpu works in original st9 compatibility mode. for the duration of the inter- rupt service routine, isr is used instead of csr, and the interrupt stack frame is identical to that of the original st9: only the pc and flags are pushed. this avoids saving the csr on the stack in the event of an interrupt, thus ensuring a faster inter- rupt response time. it is not possible for an interrupt service routine to perform inter-segment calls or jumps: these in- structions would update the csr, which, in this case, is not used (isr is used instead). the code segment size for all interrupt service routines is thus limited to 64k bytes. st9+ mode (encsr = 1) if encsr is set, isr is only used to point to the in- terrupt vector table and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and flags, and csr is then loaded with the con- tents of isr. in this case, iret will also restore csr from the stack. this approach allows interrupt service rou- tines to access the entire 4 mbytes of address space. the drawback is that the interrupt response time is slightly increased, because of the need to also save csr on the stack. full compatibility with the original st9 is lost in this case, because the interrupt stack frame is differ- ent. 3.3 interrupt priority levels the st9 supports a fully programmable interrupt priority structure. nine priority levels are available to define the channel priority relationships: C the on-chip peripheral channels and the eight external interrupt sources can be programmed within eight priority levels. each channel has a 3- bit field, prl (priority level), that defines its pri- ority level in the range from 0 (highest priority) to 7 (lowest priority). C the 9th level (top level priority) is reserved for the timer/watchdog or the external pseudo non-maskable interrupt. an interrupt service routine at this level cannot be interrupted in any arbitration mode. its mask can be both maskable (tli) or non-maskable (tlnm). 3.4 priority level arbitration the 3 bits of cpl (current priority level) in the central interrupt control register contain the pri- ority of the currently running program (cpu priori- ty). cpl is set to 7 (lowest priority) upon reset and can be modified during program execution either by software or automatically by hardware accord- ing to the selected arbitration mode. during every instruction, an arbitration phase takes place, during which, for every channel capa- ble of generating an interrupt, each priority level is compared to all the other requests (interrupts or dma). if the highest priority request is an interrupt, its prl value must be strictly lower (that is, higher pri- ority) than the cpl value stored in the cicr regis- ter (r230) in order to be acknowledged. the top level interrupt overrides every other priority. 3.4.1 priority level 7 (lowest) interrupt requests at prl level 7 cannot be ac- knowledged, as this prl value (the lowest possi- ble priority) cannot be strictly lower than the cpl value. this can be of use in a fully polled interrupt environment. 3.4.2 maximum depth of nesting no more than 8 routines can be nested. if an inter- rupt routine at level n is being serviced, no other interrupts located at level n can interrupt it. this guarantees a maximum number of 8 nested levels including the top level interrupt request. encsr bit 0 1 mode st9 compatible st9+ pushed/popped registers pc, flagr pc, flagr, csr max. code size for interrupt service routine 64kb within 1 segment no limit across segments
44/178 st92185b - interrupts priority level arbitration (contd) 3.4.3 simultaneous interrupts if two or more requests occur at the same time and at the same priority level, an on-chip daisy chain, specific to every st9 version, selects the channel with the highest position in the chain, as shown in table 5. table 5. daisy chain priority for the st92185b 3.4.4 dynamic priority level modification the main program and routines can be specifically prioritized. since the cpl is represented by 3 bits in a read/write register, it is possible to modify dy- namically the current priority value during program execution. this means that a critical section can have a higher priority with respect to other inter- rupt requests. furthermore it is possible to priori- tize even the main program execution by modify- ing the cpl during its execution. see figure 21 figure 21. example of dynamic priority level modification in nested mode 3.5 arbitration modes the st9 provides two interrupt arbitration modes: concurrent mode and nested mode. concurrent mode is the standard interrupt arbitration mode. nested mode improves the effective interrupt re- sponse time when service routine nesting is re- quired, depending on the request priority levels. the iam control bit in the cicr register selects concurrent arbitration mode or nested arbitration mode. 3.5.1 concurrent mode this mode is selected when the iam bit is cleared (reset condition). the arbitration phase, performed during every instruction, selects the request with the highest priority level. the cpl value is not modified in this mode. start of interrupt routine the interrupt cycle performs the following steps: C all maskable interrupt requests are disabled by clearing cicr.ien. C the pc low byte is pushed onto system stack. C the pc high byte is pushed onto system stack. C if encsr is set, csr is pushed onto system stack. C the flag register is pushed onto system stack. C the pc is loaded with the 16-bit vector stored in the vector table, pointed to by the ivr. C if encsr is set, csr is loaded with isr con- tents; otherwise isr is used in place of csr until iret instruction. end of interrupt routine the interrupt service routine must be ended with the iret instruction. the iret instruction exe- cutes the following operations: C the flag register is popped from system stack. C if encsr is set, csr is popped from system stack. C the pc high byte is popped from system stack. C the pc low byte is popped from system stack. C all unmasked interrupts are enabled by setting the cicr.ien bit. C if encsr is reset, csr is used instead of isr. normal program execution thus resumes at the in- terrupted instruction. all pending interrupts remain pending until the next ei instruction (even if it is executed during the interrupt service routine). note : in concurrent mode, the source priority level is only useful during the arbitration phase, where it is compared with all other priority levels and with the cpl. no trace is kept of its value during the isr. if other requests are issued during the inter- rupt service routine, once the global cicr.ien is re-enabled, they will be acknowledged regardless of the interrupt service routines priority. this may cause undesirable interrupt response sequences. highest position lowest position inta0 inta1 intb0 intb1 intc0 intc1 intd0 intd1 int0/wdt int1/standard timer int2/spi int3/ad converter int4/sync (eofvbi) int5/sync (fldst) int6 int7 6 5 4 7 priority level main cpl is set to 5 cpl=7 main int 6 cpl=6 int6 ei cpl is set to 7 cpl6 > cpl5: int6 pending interrupt 6 has priority level 6 by main program
45/178 st92185b - interrupts arbitration modes (contd) examples in the following two examples, three interrupt re- quests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service rou- tine. example 1 in the first example, (simplest case, figure 22 ) the ei instruction is not used within the interrupt serv- ice routines. this means that no new interrupt can be serviced in the middle of the current one. the interrupt routines will thus be serviced one after another, in the order of their priority, until the main program eventually resumes. figure 22. simple example of a sequence of interrupt requests with: - concurrent mode selected and - ien unchanged by the interrupt routines 6 5 4 3 2 1 0 7 priority level of main int 5 int 2 int 3 int 4 main int 5 int 4 int 3 int 2 cpl is set to 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 interrupt request
46/178 st92185b - interrupts arbitration modes (contd) example 2 in the second example, (more complex, figure 23 ), each interrupt service routine sets interrupt enable with the ei instruction at the beginning of the routine. placed here, it minimizes response time for requests with a higher priority than the one being serviced. the level 2 interrupt routine (with the highest prior- ity) will be acknowledged first, then, when the ei instruction is executed, it will be interrupted by the level 3 interrupt routine, which itself will be inter- rupted by the level 4 interrupt routine. when the level 4 interrupt routine is completed, the level 3 in- terrupt routine resumes and finally the level 2 inter- rupt routine. this results in the three interrupt serv- ice routines being executed in the opposite order of their priority. it is therefore recommended to avoid inserting the ei instruction in the interrupt service rou- tine in concurrent mode . use the ei instruc- tion only in nested mode. warning: if, in concurrent mode, interrupts are nested (by executing ei in an interrupt service routine), make sure that either encsr is set or csr=isr, otherwise the iret of the innermost in- terrupt will make the cpu use csr instead of isr before the outermost interrupt service routine is terminated, thus making the outermost routine fail. figure 23. complex example of a sequence of interrupt requests with: - concurrent mode selected - ien set to 1 during interrupt service routine execution 6 5 4 3 2 1 0 7 main int 5 int 2 int 3 int 4 int 5 int 4 int 3 int 2 cpl is set to 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 int 2 int 3 cpl = 7 cpl = 7 int 5 cpl = 7 main ei ei ei priority level of interrupt request ei
47/178 st92185b - interrupts arbitration modes (contd) 3.5.2 nested mode the difference between nested mode and con- current mode, lies in the modification of the cur- rent priority level (cpl) during interrupt process- ing. the arbitration phase is basically identical to con- current mode, however, once the request is ac- knowledged, the cpl is saved in the nested inter- rupt control register (nicr) by setting the nicr bit corresponding to the cpl value (i.e. if the cpl is 3, the bit 3 will be set). the cpl is then loaded with the priority of the re- quest just acknowledged; the next arbitration cycle is thus performed with reference to the priority of the interrupt service routine currently being exe- cuted. start of interrupt routine the interrupt cycle performs the following steps: C all maskable interrupt requests are disabled by clearing cicr.ien. C cpl is saved in the special nicr stack to hold the priority level of the suspended routine. C priority level of the acknowledged routine is stored in cpl, so that the next request priority will be compared with the one of the routine cur- rently being serviced. C the pc low byte is pushed onto system stack. C the pc high byte is pushed onto system stack. C if encsr is set, csr is pushed onto system stack. C the flag register is pushed onto system stack. C the pc is loaded with the 16-bit vector stored in the vector table, pointed to by the ivr. C if encsr is set, csr is loaded with isr con- tents; otherwise isr is used in place of csr until iret instruction. figure 24. simple example of a sequence of interrupt requests with: - nested mode - ien unchanged by the interrupt routines 6 5 4 3 2 1 0 7 main int 2 int0 int4 int3 int2 cpl is set to 7 cpl=2 cpl=7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 main int 3 cpl=3 int 6 cpl=6 int5 int 0 cpl=0 int6 int2 interrupt 6 has priority level 6 interrupt 0 has priority level 0 cpl6 > cpl3: int6 pending cpl2 < cpl4: serviced next int 2 cpl=2 int 4 cpl=4 int 5 cpl=5 priority level of interrupt request
48/178 st92185b - interrupts arbitration modes (contd) end of interrupt routine the iret interrupt return instruction executes the following steps: C the flag register is popped from system stack. C if encsr is set, csr is popped from system stack. C the pc high byte is popped from system stack. C the pc low byte is popped from system stack. C all unmasked interrupts are enabled by setting the cicr.ien bit. C the priority level of the interrupted routine is popped from the special register (nicr) and copied into cpl. C if encsr is reset, csr is used instead of isr, unless the program returns to another nested routine. the suspended routine thus resumes at the inter- rupted instruction. figure 24 contains a simple example, showing that if the ei instruction is not used in the interrupt service routines, nested and concurrent modes are equivalent. figure 25 contains a more complex example showing how nested mode allows nested interrupt processing (enabled inside the interrupt service routinesi using the ei instruction) according to their priority level. figure 25. complex example of a sequence of interrupt requests with: - nested mode - ien set to 1 during the interrupt routine execution int 2 int 3 cpl=3 int 0 cpl=0 int6 6 5 4 3 2 1 0 7 main int 5 int 4 int0 int4 int3 int2 cpl is set to 7 cpl=5 cpl=4 cpl=2 cpl=7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 int 2 int 4 cpl=2 cpl=4 int 5 cpl=5 main ei ei int 2 cpl=2 int 6 cpl=6 int5 int2 ei interrupt 6 has priority level 6 interrupt 0 has priority level 0 cpl6 > cpl3: int6 pending cpl2 < cpl4: serviced just after ei priority level of interrupt request ei
49/178 st92185b - interrupts 3.6 external interrupts the standard st9 core contains 8 external inter- rupts sources grouped into four pairs. table 6. external interrupt channel grouping each source has a trigger control bit tea0,..ted1 (r242,eitr.0,..,7 page 0) to select triggering on the rising or falling edge of the external pin. if the trigger control bit is set to 1, the corresponding pending bit ipa0,..,ipd1 (r243,eipr.0,..,7 page 0) is set on the input pin rising edge, if it is cleared, the pending bit is set on the falling edge of the in- put pin. each source can be individually masked through the corresponding control bit ima0,..,imd1 (eimr.7,..,0). see figure 27 . the priority level of the external interrupt sources can be programmed among the eight priority lev- els with the control register eiplr (r245). the pri- ority level of each pair is software defined using the bits prl2, prl1. for each pair, the even channel (a0,b0,c0,d0) of the group has the even priority level and the odd channel (a1,b1,c1,d1) has the odd (lower) priority level. figure 26. priority level examples n figure 26 shows an example of priority levels. figure 27 gives an overview of the external inter- rupt control bits and vectors. C the source of the interrupt channel inta0 can be selected between the external pin int0 (when ia0s = 1, the reset value) or the on-chip timer/ watchdog peripheral (when ia0s = 0). C inta1: by selecting ints equal to 0, the stand- ard timer is chosen as the interrupt. C the source of the interrupt channel intb0 can be selected between the external pin int2 (when (spen,bms)=(0,0)) or the spi peripheral. C intb1: setting ad-int.0 to 1 selects the adc as the interrupt source for channel intb1. C setting bit 2 of the csyct to 1 selects eofvbi interrupt as the source for intc0. setting this bit to 0 selects external interrupt on int4. C setting fsten (bit 3 of the csyct register) to 1 selects fldst interrupt for channel intc1. set- ting this bit to 0 selects external interrupt int5. interrupt channels intd0 and intd1 have an in- put pin as source. however, the input line may be multiplexed with an on-chip peripheral i/o or con- nected to an input pin that performs also another function. warning: when using channels shared by both external interrupts and peripherals, special care must be taken to configure their control registers for both peripherals and interrupts. table 7. internal/external interrupt source external interrupt channel int7 int6 intd1 intd0 int5 int4 intc1 intc0 int3 int2 intb1 intb0 int1 int0 inta1 inta0 1001001 pl2d pl1d pl2c pl1c pl2b pl1b pl2a pl1a int.d1: int.c1: 001=1 int.d0: source priority priorit y source int.a0: 010=2 int.a1: 011=3 int.b1: 101=5 int.b0: 100=4 int.c0: 000=0 eiplr vr000151 0 100=4 101=5 channel internal interrupt source external interrupt source inta0 timer/watchdog int0 inta1 standard timer none intb0 spi interrupt int2 intb1 a/d converter none intc0 eofvbi (sync inter) int4 intc1 fldst (sync inter) int5 intd0 none int6 intd1 none int7
50/178 st92185b - interrupts external interrupts (contd) figure 27. external interrupts control bits and vectors n n int a0 request vector priority level mask bit pending bit ima0 ipa0 v7 v6 v5 v4 0 0 0 0 0 1 ia0s watchdog/timer end of count int 0 pin int a1 request int b0 request int 2 pin int b1 request int c0 request int 4 pin int c1 request tec1 int 5 pin int d0 request ted0 int 6 pin int d1 request ted1 int 7 pin vector priority level mask bit pending bit ima1 ipa1 v7 v6 v5 v4 0 0 1 0 1 v7 v6 v5 v4 0 1 0 0 v7 v6 v5 v4 0 1 1 0 v7 v6 v5 v4 1 0 00 v7 v6 v5 v4 1 0 1 0 v7 v6 v5 v4 1 1 0 0 v7 v6 v5 v4 1 1 1 0 vector priority level vector priority level vector priority level vector priority level vector priority level vector priority level mask bit imb0 pending bit ipb0 pending bit ipb1 pending bit ipc0 pending bit ipc1 pending bit ipd0 pending bit ipd1 mask bit imb1 mask bit imc0 mask bit imc1 mask bit imd0 mask bit imd1 * shared channels, see warning * * spen,bms spi interrupt tea0 tec0 teb0 0,0 pl2a pl1a 1 pl2c pl1c 0 pl2b pl1b 0 pl2a pl1a 1 pl2b pl1b 0 pl2c pl1c 0 pl2d pl1d 1 pl2d pl1d 0 1 std. timer ints not connected adc 0 1 adint not connected (sync inter) eofvbi 1 0 vben fsten 1 0 fldst (sync inter) 1,x
51/178 st92185b - interrupts 3.7 top level interrupt the top level interrupt channel can be assigned either to the external pin nmi or to the timer/ watchdog according to the status of the control bit eivr.tlis (r246.2, page 0). if this bit is high (the reset condition) the source is the external pin nmi. if it is low, the source is the timer/ watchdog end of count. when the source is the nmi external pin, the control bit eivr.tltev (r246.3; page 0) selects between the rising (if set) or falling (if reset) edge generating the interrupt request. when the selected event occurs, the cicr.tlip bit (r230.6) is set. depending on the mask situation, a top level interrupt request may be generated. two kinds of masks are available, a maskable mask and a non-maskable mask. the first mask is the cicr.tli bit (r230.5): it can be set or cleared to enable or disable respectively the top level inter- rupt request. if it is enabled, the global enable in- terrupt bit, cicr.ien (r230.4) must also be ena- bled in order to allow a top level request. the second mask nicr.tlnm (r247.7) is a set- only mask. once set, it enables the top level in- terrupt request independently of the value of cicr.ien and it cannot be cleared by the pro- gram. only the processor reset cycle can clear this bit. this does not prevent the user from ignor- ing some sources due to a change in tlis. the top level interrupt service routine cannot be interrupted by any other interrupt or dma request, in any arbitration mode, not even by a subsequent top level interrupt request. warning . the interrupt machine cycle of the top level interrupt does not clear the cicr.ien bit, and the corresponding iret does not set it. fur- thermore the tli never modifies the cpl bits and the nicr register. 3.8 on-chip peripheral interrupts the general structure of the peripheral interrupt unit is described here, however each on-chip pe- ripheral has its own specific interrupt unit contain- ing one or more interrupt channels, or dma chan- nels. please refer to the specific peripheral chap- ter for the description of its interrupt features and control registers. the on-chip peripheral interrupt channels provide the following control bits: C interrupt pending bit (ip). set by hardware when the trigger event occurs. can be set/ cleared by software to generate/cancel pending interrupts and give the status for interrupt polling. C interrupt mask bit (im). if im = 0, no interrupt request is generated. if im =1 an interrupt re- quest is generated whenever ip = 1 and cicr.ien = 1. C priority level (prl, 3 bits). these bits define the current priority level, prl=0: the highest pri- ority, prl=7: the lowest priority (the interrupt cannot be acknowledged) C interrupt vector register (ivr, up to 7 bits). the ivr points to the vector table which itself contains the interrupt routine start address. figure 28. top level interrupt structure n n watchdog enable wden watchdog timer end of count nmi or tltev mux tlis tlip tlnm tli ien pending mask top level interrupt va00294 core reset request
52/178 st92185b - interrupts 3.9 interrupt response time the interrupt arbitration protocol functions com- pletely asynchronously from instruction flow and requires 5 clock cycles. one more cpuclk cycle is required when an interrupt is acknowledged. requests are sampled every 5 cpuclk cycles. if the interrupt request comes from an external pin, the trigger event must occur a minimum of one intclk cycle before the sampling time. when an arbitration results in an interrupt request being generated, the interrupt logic checks if the current instruction (which could be at any stage of execution) can be safely aborted; if this is the case, instruction execution is terminated immedi- ately and the interrupt request is serviced; if not, the cpu waits until the current instruction is termi- nated and then services the request. instruction execution can normally be aborted provided no write operation has been performed. for an interrupt deriving from an external interrupt channel, the response time between a user event and the start of the interrupt service routine can range from a minimum of 26 clock cycles to a max- imum of 55 clock cycles (div instruction), 53 clock cycles (divws and mul instructions) or 49 for other instructions. for a non-maskable top level interrupt, the re- sponse time between a user event and the start of the interrupt service routine can range from a min- imum of 22 clock cycles to a maximum of 51 clock cycles (div instruction), 49 clock cycles (divws and mul instructions) or 45 for other instructions. in order to guarantee edge detection, input signals must be kept low/high for a minimum of one intclk cycle. an interrupt machine cycle requires a basic 18 in- ternal clock cycles (cpuclk), to which must be added a further 2 clock cycles if the stack is in the register file. 2 more clock cycles must further be added if the csr is pushed (encsr =1). the interrupt machine cycle duration forms part of the two examples of interrupt response time previ- ously quoted; it includes the time required to push values on the stack, as well as interrupt vector handling. in wait for interrupt mode, a further cycle is re- quired as wake-up delay.
53/178 st92185b - interrupts 3.10 interrupt registers central interrupt control register (cicr) r230 - read/write register group: system reset value: 1000 0111 (87h) bit 7 = gcen : global counter enable. this bit enables the 16-bit multifunction timer pe- ripheral. 0: mft disabled 1: mft enabled bit 6 = tlip : top level interrupt pending . this bit is set by hardware when top level inter- rupt (tli) trigger event occurs. it is cleared by hardware when a tli is acknowledged. it can also be set by software to implement a software tli. 0: no tli pending 1: tli pending bit 5 = tli : top level interrupt. this bit is set and cleared by software. 0: a top level interrupt is generared when tlip is set, only if tlnm=1 in the nicr register (inde- pendently of the value of the ien bit). 1: a top level interrupt request is generated when ien=1 and the tlip bit are set. bit 4 = ien : interrupt enable . this bit is cleared by the interrupt machine cycle (except for a tli). it is set by the iret instruction (except for a return from tli). it is set by the ei instruction. it is cleared by the di instruction. 0: maskable interrupts disabled 1: maskable interrupts enabled note: the ien bit can also be changed by soft- ware using any instruction that operates on regis- ter cicr, however in this case, take care to avoid spurious interrupts, since ien cannot be cleared in the middle of an interrupt arbitration. only modify the ien bit when interrupts are disabled or when no peripheral can generate interrupts. for exam- ple, if the state of ien is not known in advance, and its value must be restored from a previous push of cicr on the stack, use the sequence di; pop cicr to make sure that no interrupts are be- ing arbitrated when cicr is modified. bit 3 = iam : interrupt arbitration mode . this bit is set and cleared by software. 0: concurrent mode 1: nested mode bit 2:0 = cpl[2:0]: current priority level . these bits define the current priority level. cpl=0 is the highest priority. cpl=7 is the lowest priority. these bits may be modified directly by the interrupt hardware when nested interrupt mode is used. external interrupt trigger register (eitr) r242 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = ted1 : intd1 trigger event bit 6 = ted0 : intd0 trigger event bit 5 = tec1 : intc1 trigger event bit 4 = tec0 : intc0 trigger event bit 3 = teb1 : intb1 trigger event bit 2 = teb0 : intb0 trigger event bit 1 = tea1 : inta1 trigger event bit 0 = tea0 : inta0 trigger event these bits are set and cleared by software. 0: select falling edge as interrupt trigger event 1: select rising edge as interrupt trigger event 70 gcen tlip tli ien iam cpl2 cpl1 cpl0 70 ted1 ted0 tec1 tec0 teb1 teb0 tea1 tea0
54/178 st92185b - interrupts interrupt registers (contd) external interrupt pending register (eipr) r243 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = ipd1 : intd1 interrupt pending bit bit 6 = ipd0 : intd0 interrupt pending bit bit 5 = ipc1 : intc1 interrupt pending bit bit 4 = ipc0 : intc0 interrupt pending bit bit 3 = ipb1 : intb1 interrupt pending bit bit 2 = ipb0 : intb0 interrupt pending bit bit 1 = ipa1 : inta1 interrupt pending bit bit 0 = ipa0 : inta0 interrupt pending bit these bits are set by hardware on occurrence of a trigger event (as specified in the eitr register) and are cleared by hardware on interrupt acknowl- edge. they can also be set by software to imple- ment a software interrupt. 0: no interrupt pending 1: interrupt pending external interrupt mask-bit register (eimr) r244 - read/write register page: 0 reset value: 0000 0000 (00h ) bit 7 = imd1 : intd1 interrupt mask bit 6 = imd0 : intd0 interrupt mask bit 5 = imc1 : intc1 interrupt mask bit 4 = imc0 : intc0 interrupt mask bit 3 = imb1 : intb1 interrupt mask bit 2 = imb0 : intb0 interrupt mask bit 1 = ima1 : inta1 interrupt mask bit 0 = ima0 : inta0 interrupt mask these bits are set and cleared by software. 0: interrupt masked 1: interrupt not masked (an interrupt is generated if the ipxx and ien bits = 1) external interrupt priority level register (eiplr) r245 - read/write register page: 0 reset value: 1111 1111 (ffh ) bit 7:6 = pl2d, pl1d: intd0, d1 priority level. bit 5:4 = pl2c, pl1c : intc0, c1 priority level. bit 3:2 = pl2b, pl1b : intb0, b1 priority level. bit 1:0 = pl2a, pl1a : inta0, a1 priority level. these bits are set and cleared by software. the priority is a three-bit value. the lsb is fixed by hardware at 0 for channels a0, b0, c0 and d0 and at 1 for channels a1, b1, c1 and d1. 70 ipd1 ipd0 ipc1 ipc0 ipb1 ipb0 ipa1 ipa0 70 imd1 imd0 imc1 imc0 imb1 imb0 ima1 ima0 70 pl2d pl1d pl2c pl1c pl2b pl1b pl2a pl1a pl2x pl1x hardware bit priority 00 0 1 0 (highest) 1 01 0 1 2 3 10 0 1 4 5 11 0 1 6 7 (lowest)
55/178 st92185b - interrupts interrupt registers (contd) external interrupt vector register (eivr ) r246 - read/write register page: 0 reset value: xxxx 0110b (x6h) bit 7:4 = v[7:4] : most significant nibble of external interrupt vector . these bits are not initialized by reset. for a repre- sentation of how the full vector is generated from v[7:4] and the selected external interrupt channel, refer to figure 27 . bit 3 = tltev : top level trigger event bit. this bit is set and cleared by software. 0: select falling edge as nmi trigger event 1: select rising edge as nmi trigger event bit 2 = tlis : top level input selection . this bit is set and cleared by software. 0: watchdog end of count is tl interrupt source 1: nmi is tl interrupt source bit 1 = ia0s : interrupt channel a0 selection. this bit is set and cleared by software. 0: watchdog end of count is inta0 source 1: external interrupt pin is inta0 source bit 0 = ewen : external wait enable. this bit is set and cleared by software. 0: waitn pin disabled 1: waitn pin enabled (to stretch the external memory access cycle). note: for more details on wait mode refer to the section describing the waitn pin in the external memory chapter. nested interrupt control (nicr) r247 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = tlnm : top level not maskable . this bit is set by software and cleared only by a hardware reset. 0: top level interrupt maskable. a top level re- quest is generated if the ien, tli and tlip bits =1 1: top level interrupt not maskable. a top level request is generated if the tlip bit =1 bit 6:0 = hl[6:0] : hold level x these bits are set by hardware when, in nested mode, an interrupt service routine at level x is in- terrupted from a request with higher priority (other than the top level interrupt request). they are cleared by hardware at the iret execution when the routine at level x is recovered. 70 v7 v6 v5 v4 tltev tlis iaos ewen 70 tlnm hl6 hl5 hl4 hl3 hl2 hl1 hl0
56/178 st92185b - interrupts interrupt registers (contd) external memory register 2 (emr2) r246 - read/write register page: 21 reset value: 0000 1111 (0fh) bit 7, 5:0 = reserved, keep in reset state. refer to the external memory interface chapter. bit 6 = encsr : enable code segment register. this bit is set and cleared by software. it affects the st9 cpu behaviour whenever an interrupt re- quest is issued. 0: the cpu works in original st9 compatibility mode. for the duration of the interrupt service routine, isr is used instead of csr, and the in- terrupt stack frame is identical to that of the orig- inal st9: only the pc and flags are pushed. this avoids saving the csr on the stack in the event of an interrupt, thus ensuring a faster in- terrupt response time. the drawback is that it is not possible for an interrupt service routine to perform inter-segment calls or jumps: these in- structions would update the csr, which, in this case, is not used (isr is used instead). the code segment size for all interrupt service rou- tines is thus limited to 64k bytes. 1: isr is only used to point to the interrupt vector table and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and flags, and csr is then loaded with the contents of isr. in this case, iret will also restore csr from the stack. this approach allows interrupt service routines to access the entire 4 mbytes of address space; the drawback is that the inter- rupt response time is slightly increased, be- cause of the need to also save csr on the stack. full compatibility with the original st9 is lost in this case, because the interrupt stack frame is different; this difference, however, should not affect the vast majority of programs. 70 0encsr001111
57/178 st92185b - reset and clock control unit (rccu) 4 reset and clock control unit (rccu) 4.1 introduction the reset control unit comprises two distinct sec- tions: C an oscillator that uses an external quartz crystal. C the reset/stop manager, which detects and flags hardware, software and watchdog gener- ated resets. 4.2 reset / stop manager the reset/stop manager resets the device when one of the three following triggering events occurs: C a hardware reset, consequence of a low level on the reset pin. C a software reset, consequence of an halt in- struction when enabled. C a watchdog end of count. the reset input is schmitt triggered. note: the memorized internal reset (called re- seto ) will be maintained active for a duration of 32768 oscin periods (about 8 ms for a 4 mhz crys- tal) after the external input is released (set high). this reseto internal reset signal is output on the i/o port bit p3.7 (active low) during the whole reset phase until the p3.7 configuration is changed by software. the true internal reset (to all macro- cells) will only be released 511 reference clock periods after the memorized internal reset is re- leased. it is possible to know which was the last reset triggering event, by reading bits 5 and 6 of register sdrath. figure 29. reset overview n build-up counter rccu true reset reseto memorized reset internal reset
58/178 st92185b - reset and clock control unit (rccu) 4.3 oscillator characteristics the on-chip oscillator circuit uses an inverting gate circuit with tri-state output. notes : owing to the q factor required, ceramic resonators may not provide a reliable oscillator source . the oscillator can not support quartz crystal or ce- ramic working at the third harmonic without exter- nal tank circuits. oscout must not be used to drive external cir- cuits. halt mode is set by means of the halt instruction. in this mode the parallel resistor, r, is disconnect- ed and the oscillator is disabled. this forces the in- ternal clock to a high level and oscout to a high impedance state. to exit the halt condition and restart the oscilla- tor, an external reset pulse is required. it should be noted that, if the watchdog function is enabled, a halt instruction will not disable the os- cillator. this to avoid stopping the watchdog if a halt code is executed in error. when this occurs, the cpu will be reset when the watchdog times out or when an external reset is applied. when an halt instruction is executed, the main crystal oscillator is stoped and any spurious clock are ignored. other analog systems such as the on- chip line pll or the whole video chain (sync ex- traction) must be stopped separately by the soft- ware as they will induce static consumption. table 8. oscillator transconductance figure 30. crystal oscillator note: depending on the application it may be bet- ter not to implement cl1 figure 31. internal oscillator schematic figure 32. external clock n gm min typ max ma/v 0.77 1.5 2.4 oscin oscout c l1 c l2 st9 crystal clock vr02116a vr02086a halt oscin oscout r in r out r oscin oscout clock input nc external clock vr02116b
59/178 st92185b - reset and clock control unit (rccu) oscillator characteristics (contd) the following table is relative to the fundamental quartz crystal only; assuming: C rs: parasitic series resistance of the quartz crys- tal (upper limit) C c0: parasitic capacitance of the crystal (upper limit, 7 pf) C c1,c2: maximum total capacitance on pins os- cin/oscout (value including external capaci- tance tied to the pin plus the parasitic capacitance of the board and device). table 9. crystal specification (c0 7pf) legend : rs: parasitic series resistance of the quartz crystal (up- per limit) c0: parasitic capacitance of the quartz crystal (upper limit, < 7 pf) cl1, cl2: maximum total capacitance on pins oscin and oscout (the value includes the external capaci- tance tied to the pin plus the parasitic capacitance of the board and of the device) gm: transconductance of the oscillator note .the tables are relative to the fundamental quartz crystal only (not ceramic resonator). freq. mhz. cl1=cl2= 39 pf rs max 865 4 260
60/178 st92185b - reset and clock control unit (rccu) 4.4 clock control registers mode register (moder) r235 - read/write register group: e (system) reset value: 1110 0000 (e0h) bit 7:6 = bits described in device architecture chapter. bit 5 = div2 : oscin divided by 2 . this bit controls the divide by 2 circuit which oper- ates on the oscin clock. 0: no division of oscin clock 1: oscin clock is internally divided by 2 bit 4:2 = prs[2:0] : clock prescaling . these bits define the prescaler value used to prescale cpuclk from intclk. when they are reset, the cpuclk is not prescaled, and is equal to intclk; in all other cases, the internal clock is prescaled by the value of these three bits plus one. bit 1:0 = bits described in device architecture chapter. wait control register ( wcr) r252 - read/write register page: 0 reset value: 0111 1111 (7fh) bit 7 = reserved, read as 0. bit 6 = wdgen : refer to timer/watchdog chapter. warning. resetting this bit to zero has the effect of setting the timer/watchdog to the watchdog mode. unless this is desired, this must be set to 1. bit 5:3 = wdm[2:0] : data memory wait cycles. these bits contain the number of intclk cycles to be added automatically to external data memo- ry accesses. wdm = 0 gives no additional wait cy- cles. wdm = 7 provides the maximum 7 intclk cycles (reset condition). bit 2:0 = wpm[2:0] : program memory wait cy- cles. these bits contain the number of intclk cycles to be added automatically to external program memory accesses. wpm = 0 gives no additional wait cycles, wpm = 7 provides the maximum 7 intclk cycles (reset condition). note: the number of clock cycles added refers to intclk and not to cpuclk. warning. the reset value of the wait control register gives the maximum number of wait cy- cles for external memory. to get optimum per- formance from the st9 when used in single-chip mode (no external memory) the user should write the wdm2,1,0 and wpm2,1,0 bits to 0. 70 11 div2 prs2 prs1 prs0 00 70 0 wdgen wdm2 wdm1 wdm0 wpm2 wpm1 wpm0
61/178 st92185b - reset and clock control unit (rccu) 4.5 reset control unit registers the rccu consists of two registers. they are pconf and sdrath. unless otherwise stated, unused register bits must be kept in their reset val- ue in order to avoid problems with the device be- haviour. pll configuration register ( pconf) r251 - read/write register page: 55 reset value: 0000 0111 (07h) bit 7= sresen . software reset enable . 0: rccu pll and csdu are turned off when a halt instruction is performed. 1: rccu will reset the microcontroller when a halt instruction is performed. bit 6:0= reserved bits. leave in their reset state. clock slow down unit ratio register ( sdrath) r254 - read/write register page: 55 reset value: 0010 0xxx (2xh) after software reset 0100 0xxx (4xh) after watchdog reset 0000 0000 (00h) after external reset bit 7 = reserved bit. leave in its reset state. bit 6 = wdgres . watchdog reset . wdgres is automatically set if the last reset was a watchdog reset. this is a read only bit. bit 5 = sftres . software reset . sftres is au- tomatically set if the last reset was a software re- set. this is a read only bit. bit 4:0 = reserved bits. please leave in their reset state. 70 sresen 0 0 0 0 1 1 1 70 0 wdgres sftres 0 0 x x x
62/178 st92185b - timing and clock controller 5 timing and clock controller 5.1 frequency multipliers three on-chip frequency multipliers generate the proper frequencies for: the core/real time periph- erals, the display related time base. for both the core and the display frequency mul- tipliers, a 4 bit programmable feed-back counter allows the adjustment of the multiplying factor to the application need (a 4 mhz or 8 mhz crystal is assumed). figure 33. timing and clock controller block diagram frequency multiplier fml(3:0) fmen xtal oscillator asynch. handler fmsl main clock controller divide by 2 mcfm oscin oscout fimf divide by 2 sldiv2 fmen frequency multiplier skew corrector synchronized dotck / 2 to display skwl(3:0) skwen hsync skhpls pxfm (synchronized dotck) divide by 2 (2x pixel clock for 1x width characters) 4 mhz real time divide by 2 to display storage ram (tri) div-2 moder.5 skdiv2 skdiv2 vr02095a async. handler memory wait breq wfi cpuclk prescaler 1 to 8 clock control intclk st9 clock control unit (rccu)
63/178 st92185b - timing and clock controller frequency multipliers (contd) for the off-chip filter components please refer to the required external components figure provid- ed in the first section of the data sheet. the frequency multipliers are off during and upon exiting from the reset phase. the user must pro- gram the desired multiplying factor, start the multi- plier and then wait for its stability. once the core/peripherals multiplier is stabilized, the main clock controller can be re-programmed (through the fmsl bit, mccr.6) to provide the fi- nal frequency (intclk) to the cpu. the frequency multipliers are automatically switched off when the p enters in halt mode (the halt mode forces the control register to its reset status). table 10. examples of cpu speed choice note: 24 mhz is the max. cpu authorized frequency. table 11. dotck/2 frequency choices (*) preferred values for 4/3. (**) 16/9 screen formats. note: 18 mhz is the min. dotck/2 authorized frequency. table 12. external pll filter stabilisation time crystal frequency fml (3:0) internal frequency (fimf) 4 mhz 4 10 mhz 4 mhz 5 12 mhz 4 mhz 6 14 mhz 4 mhz 7 16 mhz 4 mhz 8 18 mhz 4 mhz 11 24 mhz skw (3:0) dotck/2 8 18 mhz 9 20 mhz(*) 10 22 mhz 11 24 mhz (**) clock pin name clock name control register stabilization period mcfm main clock pll filter input pin mccr 35 ms. pxfm pixel clock pll filter input pin pxccr 35 ms
64/178 st92185b - timing and clock controller figure 34. programming the mccr figure 35. programming the skccr, pxccr set the pll frequency fml (3:0) start the pll by setting fmen = 1 validate pll as main cpu clock wait for clock stabilization example: spp #27h ;set the page ld mccr, #04h ;set fml bits to the value needed e.g. 10 mhz or mccr, #80h ;starts the pll or mccr, #40h ;validate the pll as the main cpu clock wait for stabilization time set the pll frequency skw (3:0) start the pll by setting skwen = 1 validate pll is fed to tdsram and osd wait for clock stabilization example: spp #27h ;set the page ld skccr, #04h ;set skw bits to the value needed or skccr, #80h ;starts the pll or pxccr, #80h ;pll is fed as dotck to the tdsram & osdpll wait for stabilization time
65/178 st92185b - timing and clock controller 5.2 register description main clock control register ( mccr) r253 - read/ write register page: 39 reset value: 0000 0000 (00h) the halt mode forces the register to its initializa- tion state. bit 7 = fmen . frequency multiplier enable bit. 0: fm disabled (reset state), low-power consump- tion mode. 1: fm is enabled, providing clock to the cpu. the fmen bit must be set only after programming the fml(3:0) bits. bit 6= fmsl . frequency multiplier select bit. this bit controls the choice of the st9+ core inter- nal frequency between the external crystal fre- quency and the main clock issued by the frequen- cy multiplier. in order to secure the application, the st9+ core internal frequency is automatically switched back to the external crystal frequency if the frequency multiplier is switched off (fmen =0) regardless of the value of the fmsl bit. care must be taken to reset the fmsl bit before any frequency multiplier can restart (fmen set back to 1). after reset, the external crystal frequency is al- ways sent to the st9+ core. bit 5:4 = these bits are reserved. bit 3:0 = fml[3:0] frequency bits. these 4 bits program the down-counter inserted in the feed-back loop of the frequency multiplier which generates the internal multiplied frequency fimf. the fimf value is calculated as follows : fimf = crystal frequency * [ (fml(3:0) + 1) ] /2 skew clock control register ( skccr) r254 - read/ write register page: 39 reset value: 0000 0000 (00h) the halt mode forces the register to its initializa- tion state. bit 7= skwen . frequency multiplier enable bit . 0: fm disabled (reset state), low-power consump- tion mode. 1: fm is enabled, supplying the clock to the skew corrector. the skwen bit must be set only after programming the skw(3-0) bits. bit 6= skdiv2 . divide-by-2 enable this bit determines whether a divide-by-2 down- scaling factor is applied to the output of the skew corrector. 0 = divide-by-2 enabled 1 = divide-by-2 disabled bit 5:4 = these bits are reserved. bit 3:0 = skw[3:0]. frequency bits these 4 bits program the down-counter inserted in the feedback loop of the frequency multiplier which generates the internal multiplied frequency dotck. the dotck value is calculated as fol- lows : f(dotck) = crystal frequency * [ (skw(3:0) + 1) ] 7 6 5 43210 fmen fmsl 0 0 fml3 fml2 fml1 fml0 76543210 skw en skdiv2 0 0 skw3 skw2 skw1 skw0
66/178 st92185b - timing and clock controller register description (contd) pll clock control register ( pxccr) r251 - read/write register page: 39 reset value: 0000 0000 (00h) bit 7= pxce . pixel clock enable bit. 0: pixel and tdsram interface clocks are blocked 1: pixel clock is sent to the display controller and tdsram interface. bit 6:0= these bits are reserved. slicer clock control register ( slccr) r252 - read/ write register page: 39 reset value: 0000 0000 (00h) the halt mode forces the register to its initializa- tion state. bit 7:5 = these bits are reserved. bit 4= vmod: video mode selection. this bit is used to select either 50hz or 60hz video mode. it is set and cleared by software. 0: 50 hz. 1: 60 hz. bit 3:0= these bits are reserved. 5.2.1 register mapping the timing controller has 4 dedicated registers, mapped in a st9+ register file page (the page ad- dress is 39 (27h)), as follows : 76543 210 pxce 0 0 0 0 0 0 0 76543210 0 0 0 vmod 0 0 0 0 page 39 (27h) feh skew corrector control register skccr fdh main clock control register mccr fch slicer clock control register slccr fbh pixel clock control register pxccr
67/178 st92185b - i/o ports 6 i/o ports 6.1 introduction st9 devices feature flexible individually program- mable multifunctional input/output lines. refer to the pin description chapter for specific pin alloca- tions. these lines, which are logically grouped as 8-bit ports, can be individually programmed to pro- vide digital input/output and analog input, or to connect input/output signals to the on-chip periph- erals as alternate pin functions. all ports can be in- dividually configured as an input, bi-directional, output or alternate function. in addition, pull-ups can be turned off for open-drain operation, and weak pull-ups can be turned on in their place, to avoid the need for off-chip resistive pull-ups. ports configured as open drain must never have voltage on the port pin exceeding v dd (refer to the electri- cal characteristics section). depending on the specific port, input buffers are software selectable to be ttl or cmos compatible, however on sch- mitt trigger ports, no selection is possible. 6.2 specific port configurations refer to the pin description chapter for a list of the specific port styles and reset values. 6.3 port control registers each port is associated with a data register (pxdr) and three control registers (pxc0, pxc1, pxc2). these define the port configuration and al- low dynamic configuration changes during pro- gram execution. port data and control registers are mapped into the register file as shown in fig- ure 1 . port data and control registers are treated just like any other general purpose register. there are no special instructions for port manipulation: any instruction that can address a register, can ad- dress the ports. data can be directly accessed in the port register, without passing through other memory or accumulator locations. figure 36. i/o register map group e group f page 2 group f page 3 group f page 43 system registers ffh reserved p7dr p9dr r255 feh p3c2 p7c2 p9c2 r254 fdh p3c1 p7c1 p9c1 r253 fch p3c0 p7c0 p9c0 r252 fbh reserved p6dr p8dr r251 fah p2c2 p6c2 p8c2 r250 f9h p2c1 p6c1 p8c1 r249 f8h p2c0 p6c0 p8c0 r248 f7h reserved reserved reserved r247 f6h p1c2 p5c2 r246 e5h p5dr r229 f5h p1c1 p5c1 r245 e4h p4dr r228 f4h p1c0 p5c0 r244 e3h p3dr r227 f3h reserved reserved r243 e2h p2dr r226 f2h p0c2 p4c2 r242 e1h p1dr r225 f1h p0c1 p4c1 r241 e0h p0dr r224 f0h p0c0 p4c0 r240
68/178 st92185b - i/o ports port control registers (contd) during reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output data register is set to ffh. this condition is also held after reset, except for ports 0 and 1 in rom- less devices, and can be redefined under software control. bidirectional ports without weak pull-ups are set in high impedance during reset. to ensure proper levels during reset, these ports must be externally connected to either v dd or v ss through external pull-up or pull-down resistors. other reset conditions may apply in specific st9 devices. 6.4 input/output bit configuration by programming the control bits pxc0.n and pxc1.n (see figure 2 ) it is possible to configure bit px.n as input, output, bidirectional or alternate function output, where x is the number of the i/o port, and n the bit within the port (n = 0 to 7). when programmed as input, it is possible to select the input level as ttl or cmos compatible by pro- gramming the relevant pxc2.n control bit. this option is not available on schmitt trigger ports. the output buffer can be programmed as push- pull or open-drain. a weak pull-up configuration can be used to avoid external pull-ups when programmed as bidirec- tional (except where the weak pull-up option has been permanently disabled in the pin hardware as- signment). each pin of an i/o port may assume software pro- grammable alternate functions (refer to the de- vice pin description and to section 1.5 ). to output signals from the st9 peripherals, the port must be configured as af out. on st9 devices with a/d converter(s), configure the ports used for analog inputs as af in. the basic structure of the bit px.n of a general pur- pose port px is shown in figure 3 . independently of the chosen configuration, when the user addresses the port as the destination reg- ister of an instruction, the port is written to and the data is transferred from the internal data bus to the output master latches. when the port is ad- dressed as the source register of an instruction, the port is read and the data (stored in the input latch) is transferred to the internal data bus. when px.n is programmed as an input : (see figure 4 ). C the output buffer is forced tristate. C the data present on the i/o pin is sampled into the input latch at the beginning of each instruc- tion execution. C the data stored in the output master latch is copied into the output slave latch at the end of the execution of each instruction. thus, if bit px.n is reconfigured as an output or bidirectional, the data stored in the output slave latch will be re- flected on the i/o pin.
69/178 st92185b - i/o ports input/output bit configuration (contd) figure 37. control bits n table 13. port bit configuration table (n = 0, 1... 7; x = port number) (1) for a/d converter inputs. legend: x = port n = bit af = alternate function bid = bidirectional cmos= cmos standard input levels hi-z = high impedance in = input od = open drain out = output pp = push-pull ttl = ttl standard input levels wp = weak pull-up bit 7 bit n bit 0 pxc2 pxc27 pxc2n pxc20 pxc1 pxc17 pxc1n pxc10 pxc0 pxc07 pxc0n pxc00 general purpose i/o pins a/d pins pxc2n pxc1n pxc0n 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 pxn configuration bid bid out out in in af out af out af in pxn output type wp od od pp od hi-z hi-z pp od hi-z (1) pxn input type ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) cmos (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) analog input
70/178 st92185b - i/o ports input/output bit configuration (contd) figure 38. basic structure of an i/o port pin figure 39. input configuration n n figure 40. output configuration n output slave latch output master latch input latch internal data bus i/o pin push-pull tristate open drain weak pull-up from peripheral output output input bidirectional alternate function to peripheral inputs and ttl / cmos (or schmitt trigger) interrupts alternate function input output bidirectional output master latch input latch output slave latch internal data bus i/o pin tristate to peripheral inputs and ttl / cmos (or schmitt trigger) interrupts output master latch input latch output slave latch internal data bus i/o pin open drain ttl (or schmitt trigger) push-pull to peripheral inputs and interrupts
71/178 st92185b - i/o ports input/output bit configuration (contd) when px.n is programmed as an output : ( figure 5 ) C the output buffer is turned on in an open-drain or push-pull configuration. C the data stored in the output master latch is copied both into the input latch and into the out- put slave latch, driving the i/o pin, at the end of the execution of the instruction. when px.n is programmed as bidirectional : ( figure 6 ) C the output buffer is turned on in an open-drain or weak pull-up configuration (except when dis- abled in hardware). C the data present on the i/o pin is sampled into the input latch at the beginning of the execution of the instruction. C the data stored in the output master latch is copied into the output slave latch, driving the i/ o pin, at the end of the execution of the instruc- tion. warning : due to the fact that in bidirectional mode the external pin is read instead of the output latch, particular care must be taken with arithme- tic/logic and boolean instructions performed on a bidirectional port pin. these instructions use a read-modify-write se- quence, and the result written in the port register depends on the logical level present on the exter- nal pin. this may bring unwanted modifications to the port output register content. for example: port register content, 0fh external port value, 03h (bits 3 and 2 are externally forced to 0) a bset instruction on bit 7 will return: port register content, 83h external port value, 83h (bits 3 and 2 have been cleared). to avoid this situation, it is suggested that all oper- ations on a port, using at least one bit in bidirec- tional mode, are performed on a copy of the port register, then transferring the result with a load in- struction to the i/o port. when px.n is programmed as a digital alter- nate function output : ( figure 7 ) C the output buffer is turned on in an open-drain or push-pull configuration. C the data present on the i/o pin is sampled into the input latch at the beginning of the execution of the instruction. C the signal from an on-chip function is allowed to load the output slave latch driving the i/o pin. signal timing is under control of the alternate function. if no alternate function is connected to px.n, the i/o pin is driven to a high level when in push-pull configuration, and to a high imped- ance state when in open drain configuration. figure 41. bidirectional configuration n n figure 42. alternate function configuration n n n n n n output master latch input latch output slave latch internal data bus i/o pin weak pull-up ttl (or schmitt trigger) open drain to peripheral inputs and interrupts input latch from internal data bus i/o pin open drain ttl (or schmitt trigger) push-pull peripheral output to peripheral inputs and interrupts output slave latch
72/178 st92185b - i/o ports 6.5 alternate function architecture each i/o pin may be connected to three different types of internal signal: C data bus input/output C alternate function input C alternate function output 6.5.1 pin declared as i/o a pin declared as i/o, is connected to the i/o buff- er. this pin may be an input, an output, or a bidi- rectional i/o, depending on the value stored in (pxc2, pxc1 and pxc0). 6.5.2 pin declared as an alternate function input a single pin may be directly connected to several alternate function inputs. in this case, the user must select the required input mode (with the pxc2, pxc1, pxc0 bits) and enable the selected alternate function in the control register of the peripheral. no specific port configuration is re- quired to enable an alternate function input, since the input buffer is directly connected to each alter- nate function module on the shared pin. as more than one module can use the same input, it is up to the user software to enable the required module as necessary. parallel i/os remain operational even when using an alternate function input. the exception to this is when an i/o port bit is perma- nently assigned by hardware as an a/d bit. in this case , after software programming of the bit in af- od-ttl, the alternate function output is forced to logic level 1. the analog voltage level on the cor- responding pin is directly input to the a/d (see fig- ure 8 ). figure 43. a/d input configuration 6.5.3 pin declared as an alternate function output the user must select the af out configuration using the pxc2, pxc1, pxc0 bits. several alter- nate function outputs may drive a common pin. in such case, the alternate function output signals are logically anded before driving the common pin. the user must therefore enable the required alternate function output by software. warning : when a pin is connected both to an al- ternate function output and to an alternate function input, it should be noted that the output signal will always be present on the alternate function input. 6.6 i/o status after wfi, halt and reset the status of the i/o ports during the wait for in- terrupt, halt and reset operational modes is shown in the following table. the external memory interface ports are shown separately. if only the in- ternal memory is being used and the ports are act- ing as i/o, the status is the same as shown for the other i/o ports. input latch internal data bus i/o pin tristate input buffer output slave latch output master latch towards a/d converter gnd mode ext. mem - i/o ports i/o ports p0 p1, p2, p6, p9 wfi high imped- ance or next address (de- pending on the last memory op- eration per- formed on port) next address not affected (clock outputs running) halt high imped- ance next address not affected (clock outputs stopped) reset alternate function push- pull (romless device) bidirectional weak pull-up (high im- pedance when disa- bled in hardware).
73/178 st92185b - timer/watchdog (wdt) 7 on-chip peripherals 7.1 timer/watchdog (wdt) important note: this chapter is a generic descrip- tion of the wdt peripheral. however depending on the st9 device, some or all of wdt interface signals described may not be connected to exter- nal pins. for the list of wdt pins present on the st9 device, refer to the device pinout description in the first section of the data sheet. 7.1.1 introduction the timer/watchdog (wdt) peripheral consists of a programmable 16-bit timer and an 8-bit prescal- er. it can be used, for example, to: C generate periodic interrupts C measure input signal pulse widths C request an interrupt after a set number of events C generate an output signal waveform C act as a watchdog timer to monitor system in- tegrity the main wdt registers are: C control register for the input, output and interrupt logic blocks (wdtcr) C 16-bit counter register pair (wdthr, wdtlr) C prescaler register (wdtpr) the hardware interface consists of up to five sig- nals: C wdin external clock input C wdout square wave or pwm signal output C int0 external interrupt input C nmi non-maskable interrupt input C hw0sw1 hardware/software watchdog ena- ble. figure 44. timer/watchdog block diagram int0 1 input & clock control logic inen inmd1 inmd2 wdtpr 8-bit prescaler wdtrh, wdtrl 16-bit intclk/4 wdt outmd wrout output control logic interrupt control logic end of count reset top level interrupt request outen mux wdout 1 iaos tlis inta0 request nmi 1 wdgen hw0sw1 1 wdin 1 mux downcounter clock 1 pin not present on some st9 devices .
74/178 st92185b - timer/watchdog (wdt) timer/watchdog (contd) 7.1.2 functional description 7.1.2.1 external signals the hw0sw1 pin can be used to permanently en- able watchdog mode. refer to section 0.1.3.1 . the wdin input pin can be used in one of four modes: C event counter mode C gated external input mode C triggerable input mode C retriggerable input mode the wdout output pin can be used to generate a square wave or a pulse width modulated signal. an interrupt, generated when the wdt is running as the 16-bit timer/counter, can be used as a top level interrupt or as an interrupt source connected to channel a0 of the external interrupt structure (replacing the int0 interrupt input). the counter can be driven either by an external clock, or internally by intclk divided by 4. 7.1.2.2 initialisation the prescaler (wdtpr) and counter (wdtrl, wdtrh) registers must be loaded with initial val- ues before starting the timer/counter. if this is not done, counting will start with reset values. 7.1.2.3 start/stop the st_sp bit enables downcounting. when this bit is set, the timer will start at the beginning of the following instruction. resetting this bit stops the counter. if the counter is stopped and restarted, counting will resume from the last value unless a new con- stant has been entered in the timer registers (wdtrl, wdtrh). a new constant can be written in the wdtrh, wdtrl, wdtpr registers while the counter is running. the new value of the wdtrh, wdtrl registers will be loaded at the next end of count (eoc) condition while the new value of the wdtpr register will be effective immediately. end of count is when the counter is 0. when watchdog mode is enabled the state of the st_sp bit is irrelevant. 7.1.2.4 single/continuous mode the s_c bit allows selection of single or continu- ous mode.this mode bit can be written with the timer stopped or running. it is possible to toggle the s_c bit and start the counter with the same in- struction. single mode on reaching the end of count condition, the timer stops, reloads the constant, and resets the start/ stop bit. software can check the current status by reading this bit. to restart the timer, set the start/ stop bit. note: if the timer constant has been modified dur- ing the stop period, it is reloaded at start time. continuous mode on reaching the end of count condition, the coun- ter automatically reloads the constant and restarts. it is stopped only if the start/stop bit is reset. 7.1.2.5 input section if the timer/counter input is enabled (inen bit) it can count pulses input on the wdin pin. other- wise it counts the internal clock/4. for instance, when intclk = 24mhz, the end of count rate is: 2.79 seconds for maximum count (timer const. = ffffh, prescaler const. = ffh) 166 ns for minimum count (timer const. = 0000h, prescaler const. = 00h) the input pin can be used in one of four modes: C event counter mode C gated external input mode C triggerable input mode C retriggerable input mode the mode is configurable in the wdtcr. 7.1.2.6 event counter mode in this mode the timer is driven by the external clock applied to the input pin, thus operating as an event counter. the event is defined as a high to low transition of the input signal. spacing between trailing edges should be at least 8 intclk periods (or 333ns with intclk = 24mhz). counting starts at the next input event after the st_sp bit is set and stops when the st_sp bit is reset.
75/178 st92185b - timer/watchdog (wdt) timer/watchdog (contd) 7.1.2.7 gated input mode this mode can be used for pulse width measure- ment. the timer is clocked by intclk/4, and is started and stopped by means of the input pin and the st_sp bit. when the input pin is high, the tim- er counts. when it is low, counting stops. the maximum input pin frequency is equivalent to intclk/8. 7.1.2.8 triggerable input mode the timer (clocked internally by intclk/4) is started by the following sequence: C setting the start-stop bit, followed by C a high to low transition on the input pin. to stop the timer, reset the st_sp bit. 7.1.2.9 retriggerable input mode in this mode, the timer (clocked internally by intclk/4) is started by setting the st_sp bit. a high to low transition on the input pin causes counting to restart from the initial value. when the timer is stopped (st_sp bit reset), a high to low transition of the input pin has no effect. 7.1.2.10 timer/counter output modes output modes are selected by means of the out- en (output enable) and outmd (output mode) bits of the wdtcr register. no output mode (outen = 0) the output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the i/o pin. square wave output mode (outen = 1, outmd = 0) the timer outputs a signal with a frequency equal to half the end of count repetition rate on the wd- out pin. with an intclk frequency of 20mhz, this allows a square wave signal to be generated whose period can range from 400ns to 6.7 sec- onds. pulse width modulated output mode (outen = 1, outmd = 1) the state of the wrout bit is transferred to the output pin (wdout) at the end of count, and is held until the next end of count condition. the user can thus generate pwm signals by modifying the status of the wrout pin between end of count events, based on software counters decre- mented by the timer watchdog interrupt. 7.1.3 watchdog timer operation this mode is used to detect the occurrence of a software fault, usually generated by external inter- ference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence of operation. the watchdog, when enabled, resets the mcu, unless the pro- gram executes the correct write sequence before expiry of the programmed time period. the appli- cation program must be designed so as to correct- ly write to the wdtlr watchdog register at regu- lar intervals during all phases of normal operation. 7.1.3.1 hardware watchdog/software watchdog the hw0sw1 pin (when available) selects hard- ware watchdog or software watchdog. if hw0sw1 is held low: C the watchdog is enabled by hardware immedi- ately after an external reset. (note: software re- set or watchdog reset have no effect on the watchdog enable status). C the initial counter value (ffffh) cannot be mod- ified, however software can change the prescaler value on the fly. C the wdgen bit has no effect. (note: it is not forced low). if hw0sw1 is held high, or is not present: C the watchdog can be enabled by resetting the wdgen bit. 7.1.3.2 starting the watchdog in watchdog mode the timer is clocked by intclk/4. if the watchdog is software enabled, the time base must be written in the timer registers before enter- ing watchdog mode by resetting the wdgen bit. once reset, this bit cannot be changed by soft- ware. if the watchdog is hardware enabled, the time base is fixed by the reset value of the registers. resetting wdgen causes the counter to start, re- gardless of the value of the start-stop bit. in watchdog mode, only the prescaler constant may be modified. if the end of count condition is reached a system reset is generated.
76/178 st92185b - timer/watchdog (wdt) timer/watchdog (contd) 7.1.3.3 preventing watchdog system reset in order to prevent a system reset, the sequence aah, 55h must be written to wdtlr (watchdog timer low register). once 55h has been written, the timer reloads the constant and counting re- starts from the preset value. to reload the counter, the two writing operations must be performed sequentially without inserting other instructions that modify the value of the wdtlr register between the writing operations. the maximum allowed time between two reloads of the counter depends on the watchdog timeout period. 7.1.3.4 non-stop operation in watchdog mode, a halt instruction is regarded as illegal. execution of the halt instruction stops further execution by the cpu and interrupt ac- knowledgment, but does not stop intclk, cpu- clk or the watchdog timer, which will cause a system reset when the end of count condition is reached. furthermore, st_sp, s_c and the input mode selection bits are ignored. hence, regard- less of their status, the counter always runs in continuous mode, driven by the internal clock. the output mode should not be enabled, since in this context it is meaningless. figure 45. watchdog timer mode timer start counting wri te wdtrh,wdtrl wd en=0 write aah,55h into wdtrl reset software fail (e.g. infinite loop) or peripheral fail va00220 produce count reload value count g
77/178 st92185b - timer/watchdog (wdt) timer/watchdog (contd) 7.1.4 wdt interrupts the timer/watchdog issues an interrupt request at every end of count, when this feature is ena- bled. a pair of control bits, ia0s (eivr.1, interrupt a0 se- lection bit) and tlis (eivr.2, top level input se- lection bit) allow the selection of 2 interrupt sources (timer/watchdog end of count, or external pin) handled in two different ways, as a top level non maskable interrupt (software reset), or as a source for channel a0 of the external interrupt logic. a block diagram of the interrupt logic is given in figure 3. note: software traps can be generated by setting the appropriate interrupt pending bit. table 1 below, shows all the possible configura- tions of interrupt/reset sources which relate to the timer/watchdog. a reset caused by the watchdog will set bit 6, wdgres of r242 - page 55 (clock flag regis- ter). see section clock control regis- ters . figure 46. interrupt sources table 14. interrupt configuration legend: wdg = watchdog function sw trap = software trap note: if ia0s and tlis = 0 (enabling the watchdog eoc as interrupt source for both top level and inta0 interrupts), only the inta0 interrupt is taken into account. timer watchdog reset wdgen (wcr.6) inta0 request ia0s (eivr.1) mux 0 1 int0 mux 0 1 top level interrupt request va00293 tlis (eivr.2) nmi control bits enabled sources operating mode wdgen ia0s tlis reset inta0 top level 0 0 0 0 0 0 1 1 0 1 0 1 wdg/ext reset wdg/ext reset wdg/ext reset wdg/ext reset sw trap sw trap ext pin ext pin sw trap ext pin sw trap ext pin watchdog watchdog watchdog watchdog 1 1 1 1 0 0 1 1 0 1 0 1 ext reset ext reset ext reset ext reset timer timer ext pin ext pin timer ext pin timer ext pin timer timer timer timer
78/178 st92185b - timer/watchdog (wdt) timer/watchdog (contd) 7.1.5 register description the timer/watchdog is associated with 4 registers mapped into group f, page 0 of the register file. wdthr : timer/watchdog high register wdtlr : timer/watchdog low register wdtpr : timer/watchdog prescaler register wdtcr : timer/watchdog control register three additional control bits are mapped in the fol- lowing registers on page 0: watchdog mode enable, (wcr.6) top level interrupt selection, (eivr.2) interrupt a0 channel selection, (eivr.1) note : the registers containing these bits also con- tain other functions. only the bits relevant to the operation of the timer/watchdog are shown here. counter register this 16-bit register (wdtlr, wdthr) is used to load the 16-bit counter value. the registers can be read or written on the fly. timer/watchdog high register (wdthr) r248 - read/write register page: 0 reset value: 1111 1111 (ffh) bits 7:0 = r[15:8] counter most significant bits . timer/watchdog low register (wdtlr) r249 - read/write register page: 0 reset value: 1111 1111b (ffh) bits 7:0 = r[7:0] counter least significant bits. timer/watchdog prescaler register (wdtpr) r250 - read/write register page: 0 reset value: 1111 1111 (ffh) bits 7:0 = pr[7:0] prescaler value. a programmable value from 1 (00h) to 256 (ffh). warning : in order to prevent incorrect operation of the timer/watchdog, the prescaler (wdtpr) and counter (wdtrl, wdtrh) registers must be ini- tialised before starting the timer/watchdog. if this is not done, counting will start with the reset (un-in- itialised) values. watchdog timer control register (wdtcr) r251- read/write register page: 0 reset value: 0001 0010 (12h) bit 7 = st_sp : start/stop bit . this bit is set and cleared by software. 0: stop counting 1: start counting (see warning above) bit 6 = s_c : single/continuous . this bit is set and cleared by software. 0: continuous mode 1: single mode bits 5:4 = inmd[1:2] : input mode selection bits . these bits select the input mode: 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 70 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 70 st_sp s_c inmd1 inmd2 inen outmd wrout outen inmd1 inmd2 input mode 0 0 event counter 0 1 gated input (reset value) 1 0 triggerable input 1 1 retriggerable input
79/178 st92185b - timer/watchdog (wdt) timer/watchdog (contd) bit 3 = inen : input enable . this bit is set and cleared by software. 0: disable input section 1: enable input section bit 2 = outmd : output mode. this bit is set and cleared by software. 0: the output is toggled at every end of count 1: the value of the wrout bit is transferred to the output pin on every end of count if outen=1. bit 1 = wrout : write out . the status of this bit is transferred to the output pin when outmd is set; it is user definable to al- low pwm output (on reset wrout is set). bit 0 = outen : output enable bit . this bit is set and cleared by software. 0: disable output 1: enable output wait control register (wcr) r252 - read/write register page: 0 reset value: 0111 1111 (7fh) bit 6 = wdgen : watchdog enable (active low). resetting this bit via software enters the watch- dog mode. once reset, it cannot be set anymore by the user program. at system reset, the watch- dog mode is disabled. note: this bit is ignored if the hardware watchdog option is enabled by pin hw0sw1 (if available). external interrupt vector register (eivr) r246 - read/write register page: 0 reset value: xxxx 0110 (x6h) bit 2 = tlis : top level input selection . this bit is set and cleared by software. 0: watchdog end of count is tl interrupt source 1: nmi is tl interrupt source bit 1 = ia0s : interrupt channel a0 selection. this bit is set and cleared by software. 0: watchdog end of count is inta0 source 1: external interrupt pin is inta0 source warning : to avoid spurious interrupt requests, the ia0s bit should be accessed only when the in- terrupt logic is disabled (i.e. after the di instruc- tion). it is also necessary to clear any possible in- terrupt pending requests on channel a0 before en- abling this interrupt channel. a delay instruction (e.g. a nop instruction) must be inserted between the reset of the interrupt pending bit and the ia0s write instruction. other bits are described in the interrupt section. 70 xwdgenxxxxxx 70 x x x x x tlis ia0s x
80/178 st92185b - standard timer (stim) 7.2 standard timer (stim) important note: this chapter is a generic descrip- tion of the stim peripheral. depending on the st9 device, some or all of the interface signals de- scribed may not be connected to external pins. for the list of stim pins present on the particular st9 device, refer to the pinout description in the first section of the data sheet. 7.2.1 introduction the standard timer includes a programmable 16- bit down counter and an associated 8-bit prescaler with single and continuous counting modes capa- bility. the standard timer uses an input pin (stin) and an output (stout) pin. these pins, when available, may be independent pins or connected as alternate functions of an i/o port bit. stin can be used in one of four programmable in- put modes: C event counter, C gated external input mode, C triggerable input mode, C retriggerable input mode. stout can be used to generate a square wave or pulse width modulated signal. the standard timer is composed of a 16-bit down counter with an 8-bit prescaler. the input clock to the prescaler can be driven either by an internal clock equal to intclk divided by 4, or by clock2 derived directly from the external oscilla- tor, divided by device dependent prescaler value, thus providing a stable time reference independ- ent from the pll programming or by an external clock connected to the stin pin. the standard timer end of count condition is able to generate an interrupt which is connected to one of the external interrupt channels. the end of count condition is defined as the counter underflow, whenever 00h is reached. figure 47. standard timer block diagram n stout 1 external input & clock control logic inen inmd1 inmd2 stp 8-bit prescaler sth,stl 16-bit standard timer clock outmd1 outmd2 output control logic interrupt control logic end of count ints interrupt request clock2/x stin 1 interrupt 1 downcounter (see note 2) note 2: depending on device, the source of the input & clock control logic block may be permanently connected either to stin or the rccu signal clock2/x. in devices without stin and clock2, the intclk/4 mux note 1: pin not present on all st9 devices . inen bit must be held at 0.
81/178 st92185b - standard timer (stim) standard timer (contd) 7.2.2 functional description 7.2.2.1 timer/counter control start-stop count. the st-sp bit (stc.7) is used in order to start and stop counting. an instruction which sets this bit will cause the standard timer to start counting at the beginning of the next instruc- tion. resetting this bit will stop the counter. if the counter is stopped and restarted, counting will resume from the value held at the stop condi- tion, unless a new constant has been entered in the standard timer registers during the stop peri- od. in this case, the new constant will be loaded as soon as counting is restarted. a new constant can be written in sth, stl, stp registers while the counter is running. the new value of the sth and stl registers will be loaded at the next end of count condition, while the new value of the stp register will be loaded immedi- ately. warning: in order to prevent incorrect counting of the standard timer, the prescaler (stp) and counter (stl, sth) registers must be initialised before the starting of the timer. if this is not done, counting will start with the reset values (sth=ffh, stl=ffh, stp=ffh). single/continuous mode. the s-c bit (stc.6) selects between the single or continuous mode. single mode: at the end of count, the standard timer stops, reloads the constant and resets the start/stop bit (the user programmer can inspect the timer current status by reading this bit). setting the start/stop bit will restart the counter. continuous mode: at the end of the count, the counter automatically reloads the constant and re- starts. it is only stopped by resetting the start/stop bit. the s-c bit can be written either with the timer stopped or running. it is possible to toggle the s-c bit and start the standard timer with the same in- struction. 7.2.2.2 standard timer input modes (st9 devices with standard timer input stin) bits inmd2, inmd1 and inen are used to select the input modes. the input enable (inen) bit ena- bles the input mode selected by the inmd2 and inmd1 bits. if the input is disabled (inen="0"), the values of inmd2 and inmd1 are not taken into ac- count. in this case, this unit acts as a 16-bit timer (plus prescaler) directly driven by intclk/4 and transitions on the input pin have no effect. event counter mode (inmd1 = "0", inmd2 = "0") the standard timer is driven by the signal applied to the input pin (stin) which acts as an external clock. the unit works therefore as an event coun- ter. the event is a high to low transition on stin. spacing between trailing edges should be at least the period of intclk multiplied by 8 (i.e. the max- imum standard timer input frequency is 3 mhz with intclk = 24mhz). gated input mode (inmd1 = "0", inmd2 = 1) the timer uses the internal clock (intclk divided by 4) and starts and stops the timer according to the state of stin pin. when the status of the stin is high the standard timer count operation pro- ceeds, and when low, counting is stopped. triggerable input mode (inmd1 = 1, inmd2 = 0) the standard timer is started by: a) setting the start-stop bit, and b) a high to low (low trigger) transition on stin. in order to stop the standard timer in this mode, it is only necessary to reset the start-stop bit. retriggerable input mode (inmd1 = 1, inmd2 = 1) in this mode, when the standard timer is running (with internal clock), a high to low transition on stin causes the counting to start from the last constant loaded into the stl/sth and stp regis- ters. when the standard timer is stopped (st-sp bit equal to zero), a high to low transition on stin has no effect. 7.2.2.3 time base generator (st9 devices without standard timer input stin) for devices where stin is replaced by a connec- tion to clock2, the condition (inmd1 = 0, inmd2 = 0) will allow the standard timer to gen- erate a stable time base independent from the pll programming.
82/178 st92185b - standard timer (stim) standard timer (contd) 7.2.2.4 standard timer output modes output modes are selected using 2 bits of the stc register: outmd1 and outmd2. no output mode (outmd1 = 0, outmd2 = 0) the output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the i/o pin. square wave output mode (outmd1 = 0, outmd2 = 1) the standard timer toggles the state of the stout pin on every end of count condition. with intclk = 24mhz, this allows generation of a square wave with a period ranging from 333ns to 5.59 seconds. pwm output mode (outmd1 = 1) the value of the outmd2 bit is transferred to the stout output pin at the end of count. this al- lows the user to generate pwm signals, by modi- fying the status of outmd2 between end of count events, based on software counters decremented on the standard timer interrupt. 7.2.3 interrupt selection the standard timer may generate an interrupt re- quest at every end of count. bit 2 of the stc register (ints) selects the inter- rupt source between the standard timer interrupt and the external interrupt pin. thus the standard timer interrupt uses the interrupt channel and takes the priority and vector of the external inter- rupt channel. if ints is set to 1, the standard timer interrupt is disabled; otherwise, an interrupt request is gener- ated at every end of count. note: when enabling or disabling the standard timer interrupt (writing ints in the stc register) an edge may be generated on the interrupt chan- nel, causing an unwanted interrupt. to avoid this spurious interrupt request, the ints bit should be accessed only when the interrupt log- ic is disabled (i.e. after the di instruction). it is also necessary to clear any possible interrupt pending requests on the corresponding external interrupt channel before enabling it. a delay instruction (i.e. a nop instruction) must be inserted between the reset of the interrupt pending bit and the ints write instruction. 7.2.4 register mapping depending on the st9 device there may be up to 4 standard timers (refer to the block diagram in the first section of the data sheet). each standard timer has 4 registers mapped into page 11 in group f of the register file in the register description on the following page, register addresses refer to stim0 only. note: the four standard timers are not implement- ed on all st9 devices. refer to the block diagram of the device for the number of timers. std timer register register address stim0 sth0 r240 (f0h) stl0 r241 (f1h) stp0 r242 (f2h) stc0 r243 (f3h) stim1 sth1 r244 (f4h) stl1 r245 (f5h) stp1 r246 (f6h) stc1 r247 (f7h) stim2 sth2 r248 (f8h) stl2 r249 (f9h) stp2 r250 (fah) stc2 r251 (fbh) stim3 sth3 r252 (fch) stl3 r253 (fdh) stp3 r254 (feh) stc3 r255 (ffh)
83/178 st92185b - standard timer (stim) standard timer (contd) 7.2.5 register description counter high byte register (sth) r240 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = st.[15:8] : counter high-byte. counter low byte register (stl) r241 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = st.[7:0] : counter low byte. writing to the sth and stl registers allows the user to enter the standard timer constant, while reading it provides the counters current value. thus it is possible to read the counter on-the-fly. standard timer prescaler register (stp) r242 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = stp.[7:0] : prescaler. the prescaler value for the standard timer is pro- grammed into this register. when reading the stp register, the returned value corresponds to the programmed data instead of the current data. 00h: no prescaler 01h: divide by 2 ffh: divide by 256 standard timer control register (stc) r243 - read/write register page: 11 reset value: 0001 0100 (14h) bit 7 = st-sp : start-stop bit. this bit is set and cleared by software. 0: stop counting 1: start counting bit 6 = s-c : single-continuous mode select. this bit is set and cleared by software. 0: continuous mode 1: single mode bits 5:4 = inmd[1:2] : input mode selection. these bits select the input functions as shown in section 0.1.2.2, when enabled by inen. bit 3 = inen : input enable. this bit is set and cleared by software. if neither the stin pin nor the clock2 line are present, inen must be 0. 0: input section disabled 1: input section enabled bit 2 = ints : interrupt selection. 0: standard timer interrupt enabled 1: standard timer interrupt is disabled and the ex- ternal interrupt pin is enabled. bits 1:0 = outmd[1:2] : output mode selection. these bits select the output functions as described in section 0.1.2.4. 70 st.15 st.14 st.13 st.12 st.11 st.10 st.9 st.8 70 st.7 st.6 st.5 st.4 st.3 st.2 st.1 st.0 70 stp.7 stp.6 stp.5 stp.4 stp.3 stp.2 stp.1 stp.0 70 st-sp s-c inmd1 inmd2 inen ints outmd1 outmd2 inmd1 inmd2 mode 00 event counter mode 01 gated input mode 10 triggerable mode 11 retriggerable mode outmd1 outmd2 mode 00 no output mode 01 square wave output mode 1x pwm output mode
84/178 st92185b - display storage ram interface 7.3 display storage ram interface 7.3.1 introduction the display ram (tdsram) is used to hold the osd data for display. it can be shared by the following units: C display unit (dis). this osd generator is de- scribed in a separate chapter. C cpu accesses for control. the necessary time slots are provided to each unit for realtime response. features : n memory mapped in cpu memory space n direct cpu access without significant slowdown figure 48. general block diagram vr02094b
85/178 st92185b - display storage ram interface tdsram (contd) 7.3.2 functional description the data storage ram interface (tri) manages the data flows between the different sub-units (dis- play and cpu interface) and the internal ram. a specific set of buses (8 bit data tridbus, 13 bit address triabus) is dedicated to these data flows. as this tdsram interface has to manage tv ori- ented real time signals (on-screen-display): C its timing generator uses the same frequency generator as for the display (pixel frequency multiplier), C its controller is hardware synchronized to the ba- sic horizontal and vertical sync signals got through the csync controller, C its architecture gives priority to the tv real time constraints: whenever there is any access con- tention between the cpu (only in case of direct cpu access) and one of the hardware units, the cpu automatically enters a "wait" configuration until its request is serviced. 7.3.2.1 tv line timesharing during a tv line, to maintain maximum perform- ance, a continuous cycle is run repetitively. this cycle is divided in 8 sub-cycles called "slots". this 8-slot cycle is repeated continuously until the next tv line-start occurs (horizontal sync pulse de- tected). when a horizontal sync pulse is detected, the running slot is completed and the current cycle is broken. the following naming convention is used: "cpu" stands for direct cpu access slot, "dis" stands for display reading slot. each slot represents a single byte exchange (read or write) between the td- sram memory and the other units: display reading (dis). 1 byte is read from the tdsram and sent to the display unit, the address being defined by the display address generator. cpu access (cpu). 1 byte is exchanged (read or written) between the tdsram and the cpu, the address being defined by the cpu address bus.
86/178 st92185b - display storage ram interface tdsram (contd) 7.3.3 initialisation 7.3.3.1 clock initialisation before initialising the tri, first initialise the pixel clock. refer to the application examples in the osd chapter and to the rccu chapter for a de- scription of the clock control registers. 7.3.3.2 tri initialisation it is recommended to wait for a stable clock issued from the pixel frequency multiplier before enabling the tdsram interface. use the config register to initialise and start the tri. note: the don bit can only be changed while gen=0 example: spp #0x26 ld config, #0x02 ; don,gen=0 or config, #0x01 ; set gen=1 during and after a reset, the tdsram interface is forced into its "disable" mode where the sequencer is forced into its idle state.
87/178 st92185b - display storage ram interface tdsram (contd) 7.3.4 register description ram interface configuration regis- ter (config ) r252 - read/write register page: 38 reset value: 0000 0010 (02h) bit 7:2 = reserved, keep in reset state. bit 1 = don : display on/off . 0: no display reading allowed (display slot com- pletely used for cpu access). 1: display reading enabled during the respective access slot. note: don can be changed only when the tri is off (gen = 0). < bit 0 = gen : ram interface general enable . 0: tri off. display reading and cpu accesses are not allowed. when gen=0, the automatic wait cycle insertion, while trying to access the tdsram, is disabled. 1: tri on. 70 0 0 0 0 0 0 don gen
88/178 st92185b - on screen display (osd) 7.4 on screen display (osd) 7.4.1 introduction the osd displays teletext or other character data and menus on a tv screen. in serial mode , characters are coded on one byte. the display is fully compliant with the wst tele- text level 1.5. in parallel mode , characters are coded on two bytes, one byte being the font address (character code), the second byte being used for attribute control, which can be combined with the serial at- tribute capabilities. in this mode, the display meets a significant part of the wst teletext level 2 spec- ification. in order to save memory resources (reduce sys- tem cost), two display modes are provided with ei- ther a page mode display mode (teletext stan- dard, 26 rows) or a line mode (up to 12 rows) for non teletext specific menus. the osd is seen by the st9 as a peripheral which has registers mapped in the paged register space. the character codes to be displayed are taken from the tdsram memory. they are addressed by the display with the real time sequencer through the tdsram interface character by char- acter. the font rom contains 512 characters. the stan- dard european font contains all characters re- quired to support eastern and western european languages. each character can be defined by the user with the osd screen/font editor. all fonts (except the g1 mosaic font) are fully definable by masking the pixel rom content. display is done under control of the st9 cpu and the vertical and horizontal tv synchro lines. the osd provides the red, green, blue signals and the fast blanking switching signal through four analog outputs. the three color outputs use a 3-level dac which can generate half-intensity col- ors in addition to the standard saturated colors. the display block diagram is shown on figure 1 . a smart pixel processing unit provides enhanced features such as rounding or fringe for a better pic- ture quality. other smart functions such as true scrolling and cursor modes allow designing a high quality display application. 7.4.2 general features n serial character mode supporting teletext level 1.5 n parallel character mode for tv character displays (for example channel selection or volume control menus) n 40 or 80 characters/row n full page mode: 23 rows plus 1 header and 2 status rows n line mode: up to 12 rows plus 1 header and 2 status rows. n 4/3 or 16/9 screen format n synchronization to tv deflection, by hsync and vsync or csync. n box mode: display text inside and outside box solid, transparant or blank n rounding and fringing n cursor control n concealing n scrolling n semi-transparent mode (text windowing inside video picture) n half-tone mode (reduces video intensity inside a box) n normal character size 10 x 10 dots. n other character sizes available as follows: (sh: single height, sw: single width, dh: double height, dw: double width, ds: double size) both serial and parallel mode parallel display mode only sh x sw = 10 * 10 dots sh x dw = 10 * 20 dots dh x sw = 20 * 10 dots ds=dh x dw = 20 * 20 dots
89/178 st92185b - on screen display (osd) on screen display (contd) n serial character attributes: C foreground color (8 possibilities in serial full page display mode) C background color (8 possibilities) C flash / steady C start box / end box C double height C conceal / display Cfringe C contiguous mosaic / separated mosaic C hold / release mosaic C g0 font switch (in triple g0 mode) n parallel character attributes (in parallel display mode): C underline C double height & double width C upper half-character C smooth rounding C box mode C font selection g0/extended menu C selection of 15 background colors C selection of 8 foreground colors n global screen attributes: C fine and coarse horizontal adjustment (for the whole 26 rows) C vertical adjustment (for the whole page) C blanking adjustment C default background color (up 15 colors with use of half-intensity attribute) C default foreground color (up 15 colors with use of half-intensity attribute) C semi transparent display (active only on back- ground) C translucency: osd background color mixed with video picture. C full screen color (15) C national character set selection C national character mode selection C global double height display (zooming func- tion) C global fringe enable C global rounding enable n cursor control: C horizontal position (by character) C vertical position (by row) C flash, steady or underline cursor modes C color cursor with inverted foreground / invert- ed background n scrolling control: C vertical scrolling available: programmable rolling window if normal height and 40 char/row C top-down or bottom-up shift C freeze display n character fonts: 576 different characters available: C 128 mosaic matrix characters (g1), hardware defined (64 contiguous, 64 separated). C 512 character rom fonts, all user defined: C 96-character basic character set (g0) C 128 characters shared between g2 x/26 and menu characters C 96 extended menu characters C two national character set modes (mutually exclusive rom options): single g0 mode a font combining 83 characters from the g0 basic set (latin) and 13 charac- ters selected from 15 national charac- ter subsets triple g0 mode allowing different alpha- bets three 96-character fonts (e.g. latin, arabic, cyrillic ...) mode g0 national set g2 (x26+ menu) extended menu g1 (mosaic) triple g0 3*96 n/a 128 96 64 single g0 1*83 15*13 128 96 64
90/178 st92185b - on screen display (osd) on screen display (contd) figure 49. display block diagram full screen def. backg def. foreg cur. backg shift register (10b) parallel attributes character code cur. foreg attributes decoding ram interface pixel control r g b line counter row counter pixel counter char counter vpos hpos char cursor row cursor comp 10/20 comp 10/20 gen ram add gen rom add rom mosaic pla comp vpos comp hpos fast blanking fb gen pla cmd trb mux mux l1/l1+ l1/l1+ ram interface pixel cursor control scrolling control ram @ scroll 1 row scroll n row mode ctrl char decoding control st9 access on hsync on ckpix serial/parallel attributes vr02112e tslu
91/178 st92185b - on screen display (osd) on screen display (contd) 7.4.3 functional description 7.4.3.1 screen display area the screen is divided in 26 rows of basically 40 characters. from row 1 to row 23, it is possible to display 80 characters per row with the following re- strictions: C serial mode only C no rounding or fringe the three special rows, a header and two status rows have specific meanings and behaviour. they are always displayed the same way (40 charac- ters) and at the same place. in these rows, size at- tributes, scrolling and 80-character modes are not allowed. all row content, including the header and status rows, is fully user-definable. figure 50 . definition of displayed areas figure 51. screen display area. 40/80 characters 26 lines (text page) full screen area row 0 header row 24 status row 0 row 25 status row 1
92/178 st92185b - on screen display (osd) on screen display (contd) 7.4.3.2 color processing the color of any pixel on screen is the result of a priority processing among several layers which are (going from the lowest priority to the highest one): n full screen color where nothing is processed n default background color (it assumes pixel is off) n serial background color (pixel off, but background color serial attributes activated) n parallel background color (pixel off, but background color parallel attribute activated) n default foreground color (pixel on, but no foreground attribute activated) n serial foreground color (pixel on and foreground serial attribute activated) n parallel foreground color (pixel on and foreground parallel attribute activated) color processing is also the result of register con- trol bits (for global color attributes) and color ori- ented attribute bits (from serial or parallel at- tributes), refer to the figure 0.1.4.3 7.4.3.3 pixel clock control the pixel clock is generated outside of the display macrocell by the on-chip pixel frequency multipli- er which provides great frequency flexibility con- trolled by software (refer to the rccu chapter). for example, reconfiguring the application from a 4/3 screen format to a 16/9 format is just a matter of increasing the pixel frequency (i.e. reprogram- ming the pixel frequency multiplier to its new val- ue). the output signal of the pixel frequency multiplier is rephased by the skew corrector to be perfectly in phase with the horizontal sync signal which drives the display. 7.4.3.4 display character each character is made up of a 10 x 10 dots ma- trix. all character matrix contents are fully user de- finable and are stored in the pixel rom (except the g1 mosaic set which is hardware defined). a set of colors defines the final color of the current pixel. in general, the character matrix content is dis- played as it is, the pixel processing adding the shape and the color information received from the current attributes. only three kinds of attributes al- ter the displayed pixel. they are the following: 7.4.3.5 rounding rounding can be enabled for the whole display us- ing the gre global attribute bit (see figure 1 ) in this effect one half-dot is added in order to smooth the diagonal lines. this processing is built into the hardware. the half-dot is painted as foreground. this half-dot is field-sensitive for minimum vertical size ( figure 4 ). an extra smooth rounding capability is also built- in (see figure 5 ). in smooth rounding, a pixel is added even if dots make an l. this capability is activated using a parallel attribute (see table 4 ) 7.4.3.6 underline in this effect the last tv line of the character is dis- played as foreground ( figure 4 ). 7.4.3.7 fringe the fringe is a half-dot black border surrounding completely the character foreground. this half-dot is field sensitive for minimum vertical size ( figure 4 ). 7.4.3.8 translucency certain video processors are able to mix the rgb and video signals. this function of the chroma pro- cessor is then driven by the tslu output pin of the st9 device. see figure 7 . 7.4.3.9 half-tone if the ht signal is activated, for example, while a text box is displayed and a transparant back- ground selected for all the display (mm bit =1 in the fsccr register), the ht signal performs a contrast reduction to the background inside the box. see figure 8 .
93/178 st92185b - on screen display (osd) on screen display (contd) figure 52. display character scheme figure 53. rounding and fringe effects backgroun d foreground fringe fringe mode normal mode rounding mode underline background foreground smooth rounding vr02112b dot (four pixels) added pixel smooth rounding effect global rounding effect fringe effect added pixel added pixel
94/178 st92185b - on screen display (osd) on screen display (contd) 7.4.4 programming the display all the characteristics of the display are managed by programmable attributes: n global attributes n serial attributes n parallel attributes (active until a superseding serial or parallel attribute). n cursor control n scrolling control 7.4.4.1 global attributes these global attributes are defined through their corresponding registers (see the register descrip- tion). table 15. global attributes global attributes description control register display enable (de) 0= display off (default) 1= display on dcm0r r250 (fah) page 32 4/3 or 16/9 format (sf) 0= 4/3 screen format (default) 1= 16/9 screen format dcm0r conceal enable (ce) 0= reveal any text defined as concealed by serial attributes (default) 1= conceal any text defined as concealed by serial attributes dcm0r fringe enable (fre) 0= fringe disabled (default) 1= if swe in ncsr register is reset, it acts as fringe enable (toggle with serial attribute 1bh). active on the whole page but not in 80-character mode. dcm0r global fringe enable (gfr) 0= global fringe mode off 1= display all text in page in fringe mode dcm0r global rounding enable (gre) 0= disabled (default) 1= rounding active on the whole page but not in 80-character mode. dcm0r semi-transparent mode (ste) 0=disabled (default) 1=enabled the fast blanking signal is toggled with the double pixel clock rate on back- ground and full screen area in 40 character mode. note: semi-transparent mode shows a visible grid on screen. dcm0r translucency (htc and tsle) the tslu signal is active when the osd displays the background and full screen area and is inactive during foreground or if no display. this output pin is used with a chroma processor to mix the video input with the rgb to get full translucency. ncsr r245 (f5h) page 32 and fsc- cr r243 page 32 half-tone (htc and tsle) the ht signal is active when the osd displays the background and full screen area and is inactive during foreground or if no display. the ht signal is used with a video processor to perform a contrast reduction. ncsr r245 (f5h) page 32 and fsc- cr r243 page 32 40/80 chars/row (s/d) 0=single page (40 characters per row) (default) 1= two pages are displayed contiguously (80 characters per row). in this mode, only serial mode is available. dcm0r fast blanking active level 0=display when fast blanking output is low (default) 1=display when fast blanking output is high dcm1r r251 (fbh) page 32 serial/parallel mode (spm) 0= serial mode (default) 1= parallel mode dcm1r page or line display mode (pm) 0 = full page mode (default) 23 lines plus 1 header and two status lines. 1= line mode dcm1r
95/178 st92185b - on screen display (osd) on screen display (contd) table 16. global attributes (contd) global attributes description control register box control modetext in/ out text in/ text out box configurable with 3 bits. refer to fsccr register de- scription for details. fsccr r243 (f3h) page 32 vertical adjustment refer to the register description for bit settings. active on the whole page, this setting adjusts the vertical delay between the rising edge of vsync and the beginning of the display area. the display color in this delay adjustment area is defined by the full screen color. vposr r242 (f2h) page 32 horizontal adjustment refer to the register description for bit settings. active on the whole page, this adjustment is the horizontal delay between the rising edge of hsync and the beginning of the display area. the display in this delay area is the full row color. two kinds of horizontal adjustment are available. when the tube is in a 4/3 format, only a horizontal delay is necessary before starting the active dis- play area. when the tube is in 16/9 format, an additional horizontal adjust- ment is necessary to keep the display area centered on the screen. hposr r241 (f1h) page 32 national character subset selection refer to the register description for bit settings. chooses which national font sub-set is to be used with the g0 character set. ncsr r245 (f5h) page 32 single g0 or triple g0 mode selection 0 = single g0 character set mode (default) 1 = triple g0 character set mode in applications with multiple alphabets in the same display, it is possible to switch from one character set to another on the fly (see serial attributes). ncsr global double height active on the whole page with header, but not on the status rows. when global double height is active, either the top half or the bottom half of the screen is visible. sclr r248 (f8h) and schr r249 (f9h) page 32 background default color this color is displayed as background color if no serial or parallel attributes are defined for the displayed row. dcr r240 (f0h) page 33 foreground default color this color is displayed as foreground color if no serial or parallel attributes are defined for the displayed row. these default colors are selected at each beginning of a line and are defined by means of the corresponding register. dcr full screen color color displayed outside of the vertical display area. fsccr r243 (f3h) page 32
96/178 st92185b - on screen display (osd) on screen display (contd) figure 54. semi-transparent display scheme and fast blanking behaviour figure 55. translucent display scheme normal display semi transparent display line 3 field odd line 4 field even solid background solid foreground + rounding video fringe ckpix r, g, b fb ckpix r, g, b fb ckpix r, g, b fb ckpix r, g, b fb vr02112c line 3 semi transparant display line 3 normal display line 4 semi transparant display line 4 normal display rgb video line 3 normal display line 3 ckpix fb r, g, b(40c) solid background solid foreground + rounding video fringe t slu vr02112 j
97/178 st92185b - on screen display (osd) on screen display (contd) figure 56. half-tone display scheme video processor contrast reduction internal red internal green internal blue rout gout bout rgb switch st9 mcu ht r g fb b
98/178 st92185b - on screen display (osd) on screen display (contd) 7.4.4.2 row attributes the header and status row attributes are set using the hscr r244 (f4h) page 32 register. the row enable bits as set in registers de0r .. 2 r253 ..255 page 32. header enable when the display is in line mode, row 0, called the header, is also usable. it no longer acts as a head- er but simply as an additional row. status row enable the display of the two status rows can be enabled individually. row enable bits 1 bit per row, for rows from 1 to 23, in page mode. serial attributes serial mode is selected by resetting the spm bit in register dcm1r r251 (fbh) page 32. serial attributes are active until the end of the line or a superseding serial attribute. in this display mode, the attribute code and the character code are in the same memory area ( fig- ure 9 ). the attribute takes the place of an alpha charac- ter, and the osd displays a space character de- fined on 1 byte in serial mode: figure 57. example of a row in serial mode default foreground default background length of row = 40 characters global a r d o z z a a a a a propagation display a r d o z z sc a a a a a bb sty fh foreground color attribute characters black background attribute steady attribute flashing attribute memory location flashing can be half intensity vr02115a
99/178 st92185b - on screen display (osd) on screen display (contd) table 17. serial attribute codes notes : (1) presumed at the start of each display row or can be defined in global register (2) action set at (on current character) others are set after (on next character) (3) always active (even in full page serial mode, i.e. for text level 1) (4) toggles action if the fringe enable is set (bit 5 in register dcm0r r250 (fah) page 32. selects a second g0 if the switch enable bit is set (bit 5 in register ncsr r245 (f5h) page 32) flash : (/= steady) the next characters are dis- played with the foreground color alternatively equal to background and foreground on a period based on vsync (32 vsync: foreground, 16 vsync: background) until a steady serial attribute. fringe : if the fringe enable bit is set in the global attribute register dcm0r r250 (fah) page 32, the next characters are displayed with a black fringe (half dot) until the decoding of another fringe at- tribute coded 1bh (toggle effect). conceal : (/= reveal) the next characters are dis- played as space characters (background color) until a foreground color character is encountered. conceal mode is set by the conceal enable control bit in the register dcm0r r250 (fah) page 32. boxing : a part of the page (where this bit is active) is inserted in a specific window depending on 3 control bits defined in the fsccr register. (see figure 11 ) to respect the teletext norm , the box in serial mode, starts when two box-on attributes are en- countered, and stops when two box-offs are en- countered. double height : the upper halves of the charac- ters are displayed in the current row, the corre- sponding lower halves of characters are displayed (with same display attributes) in the next row (in- formation received for this row must be ignored). note: when a serial double height attribute is de- coded in row 23, the characters of the first status row are not displayed. to avoid this effect, remove the serial double height attribute from row 23. figure 58. mosaic characters note : hold mosaic: (/= release) the last mosaic character is repeated once instead of the current space character. b[7:3] 00000 00001 00010 00011 b[2:0] foreground color (alpha chars) foreground color (mosaic chars) 000 black flash black (3) conceal (2) 001 red steady (1, 2) red contiguous mosaic (1, 2) 010 green box off (1) green separated mosaic (2) 011 yellow box on yellow fringe or 2nd g0 font (3, 4) 100 blue normal height (1,2) blue black background (1, 2) 101 magenta double height magenta new background (2) 110 cyan cyan hold mosaic (2) 111 white (1) white release mosaic (1) contiguous mosaic separated mosaic
100/178 st92185b - on screen display (osd) on screen display (contd) figure 59. example of boxing attribute in serial mode figure 60. example of double height attribute in serial mode . default foreground default background length of row = 40 characters propagation b o x > < display b o x > < bo a a bo box-on attribute memory location bf bf box-off attribute bb a nb sc text inside box is visible* text outside box not displayed* vr02115b *depending on fsccr oz d r a z 3 contiguous rows displayed in serial mode on screen, the 2nd line is overlapped display memory location i d d e n h 2 6 1 4 5 3 b f a d e c dh ns r d o z z a a r d o z z sc a a a a a bb sty fh b f a d e c a r d o z z a a a a a flashing vr02115c
101/178 st92185b - on screen display (osd) on screen display (contd) 7.4.4.3 parallel attributes figure 61. example of row in parallel mode each character is defined on 2 bytes in parallel mode (see figure 13 .) parallel mode is selected by setting the spm bit in the dcm1r register r251 (fbh) page 32. it requires 2 bytes per character. display charac- ters are coded through a second byte processed in parallel with the character code. it does not handle teletext and is used mainly for tv menus (e.g. for channel searching or volume control). the attribute can be one of two types defined by most significant bit ( ps ): C color attribute C shape attribute us : underline / separate mosaic graphics (see above). dh : double height: the half character is displayed in the current row depending on the upper height control bit. the double height action is not propa- gated in the row. note: when a parallel double height attribute is decoded in row 23, the characters of the first sta- tus row are not affected and are still displayed. uh : upper half. this bit is active when the current- ly displayed row writes the upper half-character in case of double height or double size attribute. dw : double width (see above). bx : boxing window. sr : smooth rounding. fr, fg, fb : foreground color. br, bg, bb : background color. hi : half intensity (background only). css : character extended menu code selection. ps : parallel attribute selection a r d o z z a a a a a a * * * background (half intensity) foreground (full intensity) characters location display propagation default foreground default background global attributes location a r d o z z a a a a a a * * * vr02115d
102/178 st92185b - on screen display (osd) on screen display (contd) table 18. parallel color and shape attributes. double size : (available in parallel mode or in line mode) by setting double width plus double height at- tributes. figure 62. parallel color and shape attributes bit name function remarks 0 br background red 1 bg background green 2 bb background blue 3 hi half-intensity only for background. 4 fr foreground red 5 fg foreground green 6 fb foreground blue 7 ps= 0 parallel attribute selection color mode of parallel attributes 0 css character set selection g2-menu characters or g1/extended menu charac- ters selection 1 us underline/seperated mosaic dual function depending on character code 2 dh double height the character is 20 pixels high . 3 dw double width the character is 20 pixels wide. available in parallel mode or in line mode. characters are stretched hor- izontally, to occupy in addition, the next character space. it is possible to mix it with double height. to display a double width character the attribute must be double width on the character and simple width on the next which can be a serial attribute. in this case the first character is memorised. if two double width attributes are on two adjacent characters, the first half of the second is displayed instead of the second half of the first one. 4 uh upper half character (if 1) active only if double height or size requested 5 bx box mode boxing window created (if 1) 6 sr smooth rounding special rounding effect (see figure 5 ) 7 ps= 1 parallel attribute selection shape mode of parallel attributes character location attribute location a 31 b 4f a b a b a 31 b 88 80 dw ss vr02115e
103/178 st92185b - on screen display (osd) on screen display (contd) 7.4.4.4 font selection using parallel attributes parallel attributes have an immediate effect. they are applied to the associated character. these at- tributes can also have a serial effect, the defined attribute being still defined on the following charac- ters: this is known as attribute propagation. shape attributes (us,dh,bx,sr) are propagated when ps is toggled to 0. in the same way, color at- tributes are propagated when ps is toggled to 1. css has two kinds of behaviour: C if ps is set once, the css attribute is applied on the current character only. C if ps is set twice, the css of the first character with ps=1 is propagated. note: the value stored as a preceding css value is forced when alpha or mosaic color serial at- tributes are used. alpha serial attributes reset the memorized css: mosaic serial attributes set the memorized css. table 19. font selection using parallel attributes in the example in table 6 ,, a string of six charac- ters is displayed. in the line display with we can see that, starting from char(n) and ending with char n+2, the css setting made at char (n-2) is propagated. table 20. example of character set selection parallel attribute character code character definition ps= 0 00..1f 32 control characters (serial attributes function table) 20..7f 96 basic characters chosen from g0 or g1 font 80..ff 128 extended characters g2-based x/26 and menu characters ps= 1 css used for character set selection 00..1f 32 control characters (serial attributes function table) 20..7f css= 0: g0 or g1 selection depending on color serial attribute css= 1: g1 selection 80..ff css= 0: select g2-based x/26 + menu css= 1: select extended menu + 32 reserved characters char(n-2) char(n-1) char(n) char(n+1) char(n+2) char(n+3) ps= 1 1 0 0 1 1 css= cssn-2 cssn-1 none none cssn+2 cssn+3 display with cssn-2 cssn-1 cssn-2 cssn-2 cssn+2 cssn+3 stored css cssn-2 cssn-2 cssn-2 cssn-2 cssn-2 cssn+2
104/178 st92185b - on screen display (osd) on screen display (contd) figure 63. parallel mode display example 1 showing character and attribute byte pairs: parallel mode display example 2 : ram content in parallel mode aa sa b anf b i a characters x ss : simple size b7 = 0 dw : double width b7 = 1 a a ds : double size b7 = 1 nc : new colour b7 = 0 a nf i i a a dw dw nc parallel attribute ss ss nc dw ss ss ss uh=1 ds uh=0 nc dh uh=1 dh uh=0 nc nf nf a a display a a a a a b a a a a ds nc nc nc nc nf : new foreground (serial attribute) sa : serial attribute dh uh=1 dh uh =0 vr02112f e m nu s s 1 t reble b a
105/178 st92185b - on screen display (osd) on screen display (contd) 7.4.4.5 rules when using size attributes secondary effects can be generated when the shape format is not respected. the 3 figures below describe the combination of parallel size attributes to obtain the different char- acter sizes: double width double height double size 7.4.4.6 example of using double width attribute in parallel mode, double width on character can be obtained using the following rule ( figure 16 ): it is important to set double width (bit 3 of the shape attribute) on the current character attribute and single size on the following one. the second character location can be either a serial attribute or another character. on the contrary, if a new color or a double width attribute is set in the second attribute location, the second part of the character is overlapped. figure 64. double width examples attributes location characters location double width a new foreground (serial attribute) nf a ss dw simple size double width 1 row double width a b a nc dw new color double width new foreground (parallel attribute) 1 row b first half of the second character is displayed vr02115g
106/178 st92185b - on screen display (osd) on screen display (contd) 7.4.4.7 example of using double height attribute in parallel mode, double height characters can be obtained as follows. the double height attribute concerns two consecutive rows. repeat the char- acter to magnify in the two rows. set bit 2 dh of the shape attribute in the two locations and set or reset bit 4 uh to define if it is the top or bottom half-character. figure 65. double height example vr02115h display new color 2 rows double height upper half dh uh=1 dh uh=0 attributs location characters location a b b double height lower half double height a shape propagation with color b previous/default color a
107/178 st92185b - on screen display (osd) on screen display (contd) 7.4.4.8 example of using double size attribute in parallel mode, double size characters can be obtained as follows. this attribute concerns two consecutive rows. the character to magnify must be repeated on the two rows. bits 2 and 3 of the shape attribute must be set on the two locations. in addition bit 4 must be set or reset to define the top or bottom half-character. figure 66. double size examples display attribute location character location double size double height 2 rows double size upper half dh ds uh=1 dh ds uh=0 double size lower half a a nf nf a double height vr02115j
108/178 st92185b - on screen display (osd) on screen display (contd) 7.4.4.9 example of using underline attribute in parallel mode, the underline mode on character can be obtained simply by setting the bit 1 us of the shape attribute. to underline double height characters, set the us bit on the attribute associat- ed with the lower part of the character. the underline attribute is ignored in the upper half- character. figure 67. underline example double height 2 rows dh uh=1 dh uh=0 display attribute location character location u u l l u l dh uh=1 dh uh=0 underline (us=1) vr02115k underline (us=1)
109/178 st92185b - on screen display (osd) on screen display (contd) 7.4.4.10 attribute rules the default colors for foreground and background are defined through the register dcr r240 (f0h) page 33. a display defined in parallel mode can accept a se- rial color attribute, and propagation is available un- til a new color attribute (serial or parallel) is en- countered. n rule for shape attributes: C in parallel mode, shape attributes are not propagated on the following characters of the row except if this character has a colour at- tribute. the propagation lasts as long as a co- lour attribute is applied to a character. C in parallel mode, the double height (bit 2 of the shape attribute) is active only on its own char- acter. setting one double height attribute does not cover the following characters of the row (different from double height in serial mode). figure 68. rule for serial and parallel color combination highest priority defined in tdsram defined in tdsram defined in page register lowest priority parallel color serial color default color
110/178 st92185b - on screen display (osd) on screen display (contd) 7.4.4.11 cursor control n horizontal position (by character) n vertical position (by row) n color or underline cursor modes n color cursor with inverted foreground / inverted background n flash or steady mode color cursor cursor display is controlled using two registers: C cursor horizontal position r246 (f6h) page 32 C cursor vertical position r247 (f7h) page 32. notes : 1. cursor operation in underline mode: any screen location where the foreground color is identical to the background color behaves as a lost cursor (i.e. cursor not visible). assuming a serial mode display, the screen location placed on the lower row after a double height character will lead to a lost cursor. 2. ghost fringing: assuming a cursor operation in color inversion mode, assuming a serial mode display, assuming the fringe is activated, the screen location placed on the lower row after a double height character may show a ghost fringing effect (the ghost color being an inverted background one). 3. static or flash cursor mode: the horizontal cur- sor value indicates the character position (i.e. first character pointed with a 1 value); in underline mode, the horizontal cursor value gives the position minus 1. 7.4.5 vertical scrolling control n top-down or bottom-up shift n freeze display function n shift speed control n double height display scrolling scrolling is performed in a programmable rolling window if the characters are in normal height. in line mode, the scrolling window must be entire- ly filled by programmed rows (each scrolled loca- tion is defined by one of the 11 available rows). notes: 1. 80-characters combined with scrolling can only be used in line mode 2. in parallel (level 1+) mode, scrolling is possible without serial attributes ds and dh. use these two registers to control scrolling: C scrolling control low r248 (f8h) page 32 C scrolling control high r249 (f9h) page 32 7.4.5.1 rgb & fb dac and tslu outputs the r, g, b and fb pins of the st92195/ st92r195 are analog outputs controlled by true digital to analog converters. these outputs are specially designed to directly drive the video pro- cessor. the r, g and b outputs are referred to ground and they can drive up to 1.0v; they are loaded on- chip by a 0.5k ohms typical load. the effective dac output level is controlled by a 3 bit digital code issued by the display control logic with respect to the real time value of r, g or b and the half-intensity control bit, as follows: the fb (fast switch) output is also referred to ground and can drive up to 3.0v with an on-chip 0.5k ohm load. this analog fb output provides the best phase matching with the r, g, b signals. an example of the fast blanking signal is shown in figure 6 . the tlsu pin is a digital output (0-5v). r/g/b dac code display aspect during fb 0 0 0 no color 0 1 1 half- intensity color 1 1 1 full- intensity color
111/178 st92185b - on screen display (osd) on screen display (contd) 7.4.6 display memory mapping examples the display content is stored in tdsram, (2 to 8k bytes starting at address 8000h). use register tdpr r252 (fch) page 32 to address the memo- ry blocks containing the display data. two 4-bit ad- dress pointers (bits pg and hs) must be given that point to separate blocks containing the display page and the header/status rows. alternatively, the pg and hs pointers can be writ- ten to the tdppr r246 page 33 and tdhspr r247 page 33 registers. 7.4.6.1 building a serial mode full page 40- char display page location : the 1 kbyte block of page content is stored in the tdsram location pointed to by the pg3..pg0 bits. header & status rows location: the 0.5 kbyte block containing the header, status row 0 and status row 1 is pointed to by the hs3..hs0 bits. row scrolling buffer location: the scrolling buffer corresponds to the 40 bytes following the row 23 when the scrolling feature is used. figure 69. serial mode (40 characters) - page mapping figure 70. serial mode (40 characters) - header and status mapping 1k tdsram row 1 row 23 scrolling buffer free space resolution 1k bytes block number(1k) tdsram address (hex) tdpr value (hex) pg3..pg0 0 8000 0 1 8400 2 2 8800 4 3 8c00 6 4 9000 8 5 9400 a 6 9800 c 7 9c00 e 6k 2k 8k 0.5k tdsram header status row 0 free space resolution 0.5k bytes block number (0.5k) tdsram address (hex.) tdpr value (hex.) hs3..hs0 0 8000 0 1 8200 1 2 8400 2 3 8600 3 4 8800 4 5 8a00 5 6 8c00 6 7 8e00 7 8 9000 8 9 9200 9 10 9400 a 11 9600 b 12 9800 c 13 9a00 d 14 9c00 e 15 9e00 f status row 1 6k 2k 8k
112/178 st92185b - on screen display (osd) on screen display (contd) 7.4.6.2 building a parallel mode, 40-char, full page display page location: the pair of adjacent 1 kbyte blocks of page con- tent is stored in the tdsram location pointed to by the pg3..pg0 bits. the first block contains the characters, the second block contains the attribute bytes. header & status rows location: the 0.5 kbyte block containing the header, status row 0 and status row 1 is pointed to by the hs3..hs0 bits. the header/status attributes are stored in this block at offset 80h. row scrolling buffer location: the scrolling buffer corresponds to the 40 bytes following row 23 when the scrolling feature is used. figure 71. parallel mode (40 characters) - page mapping figure 72. parallel mode (40 characters) - header and status mapping 1k tdsram row 1 char. row 23 char. scrolling buffer free space resolution 2k bytes block number (2k) tdsram address (hex) char. tdsram address (hex) attr. tdpr value (hex) pg3..pg0 0 8000 8400 0 1 8800 8c00 4 2 9000 9400 8 3 9800 9c00 c 1k tdsram row 1 attr. row 23 attr. scrolling buffer free space 6k 2k 8k block number (0.5k) tdsram address (hex) tdpr value (hex) hs3..hs0 0 8000 0 1 8200 1 2 8400 2 3 8600 3 4 8800 4 5 8a00 5 6 8c00 6 7 8e00 7 8 9000 8 9 9200 9 10 9400 a 11 9600 b 12 9800 c 13 9a00 d 14 9c00 e 15 9e00 f 0.5k tdsram header char. resolution 0.5k bytes status row 0 char. status row 1 char. free space header attr. status row 0 attr. status row 1 attr. free space 80h 6k 2k 8k
113/178 st92185b - on screen display (osd) on screen display (contd) 7.4.6.3 building a serial mode, 40-char, line mode display half-page location: the 0.5 kbyte block of half-page content is stored in the tdsram location pointed to by the pg3..pg0 bits. header & status rows location: the 0.5 kbyte block containing the header, status row 0 and status row 1 is pointed to by the hs3..hs0 bits. the row attribute (row count) is stored in this block at offset 100h and contains 12 bytes for line mode (see dcm1r register descrip- tion). row scrolling buffer location: the scrolling buffer corresponds to row 12 when the scrolling feature is used (in this case 11 rows are scrolled). figure 73. serial (40 characters) line mode mapping 0.5k tdsram row 1 row 11 row 12/ scrolling buffer free space resolution 0.5k bytes see figure 22 for address values 0.5k tdsram header char. resolution 0.5k bytes status row 0 status row 1 free space row attr. free space 100h block number (0.5k) tdsram address (hex.) tdpr value (hex.) pg3..pg0 0 8000 0 1 8200 1 2 8400 2 3 8600 3 4 8800 4 5 8a00 5 6 8c00 6 7 8e00 7 8 9000 8 9 9200 9 10 9400 a 11 9600 b 12 9800 c 13 9a00 d 14 9c00 e 15 9e00 f 6k 2k 8k
114/178 st92185b - on screen display (osd) on screen display (contd) 7.4.6.4 building a parallel mode, 40 char, line mode display half-page location: the pair of adjacent 0.5 kbyte blocks of half page content is stored in the tdsram location pointed to by the pg3..pg0 bits. one block contains the characters, the other block contains the attribute bytes. header & status rows location: the 0.5 kbyte block containing the header, status row 0 and status row 1 is pointed to by the hs3..hs0 bits. the header/status attributes are stored in this block at offset 80h. the row attribute (row count) is stored in this block at offset 100h and contains 12 bytes for line mode (see dcm1r register description). row scrolling buffer location: the scrolling buffer corresponds to the row 12 when the scrolling feature is used (in this case 11 rows are scrolled). figure 74. parallel (40 characters) line mode mapping see figure 22 for address values resolution 1k bytes see figure 21 for address values 0.5k tdsram header char. resolution 0.5k bytes status row 0 status row 1 free space header attr. status row 0 status row 1 free space free space row attr. 80h 100h 0.5k tdsram 0.5k tdsram row 1 attr. row 11 attr. free space row 12/scrolling buffer row 1 char. row 11 char. free space row 12/scrolling buffer
115/178 st92185b - on screen display (osd) on screen display (contd) 7.4.6.5 building a serial mode, 80 char, full page display half-page location: the pair of adjacent 1 kbyte blocks of page con- tent is stored in the tdsram location pointed to by the pg3..pg0 bits. the first block contains the left side of the page, the second block contains the right side of the page. header & status rows location: the 0.5 kbyte block containing the header, status row 0 and status row 1 is pointed to by the hs3..hs0 bits. row scrolling buffer location: the scrolling buffer corresponds to the 40 bytes following the row 23 when the scrolling feature is used. figure 75. serial mode (80 characters) - page mapping see figure 22 for address values 1k tdsram row 1 left row 23 resolution 2k bytes 1k tdsram row 1 right see figure 23 for address values row 23 0.5k tdsram header resolution 0.5k bytes status row 0 status row 1 free space free space free space scrolling buffer scrolling buffer
116/178 st92185b - on screen display (osd) on screen display (contd) 7.4.6.6 building a serial mode, 80 char, line mode display half-page location: the pair of 0.5 kbyte blocks of half page content is stored in the tdsram location pointed to by the pg3..pg0 bits. the first block contains the left half rows, the other block contains the right half rows. header/status rows location: the 0.5 kbyte block containing the header, status row 0 and status row 1 is pointed to by the hs3..hs0 bits. the row attribute (row count) is stored in this block at offset 100h and contains 12 bytes for line mode (see dcm1r register description). row scrolling buffer location: the scrolling buffer corresponds to row 12 when the scrolling feature is used (in this case 11 rows are scrolled). figure 76. serial (80 characters) line mode mapping figure 77. serial (80 characters) line mode - header and status mapping 0.5k tdsram resolution 1k bytes block number(1k) tdsram address left (hex) tdsram address right (hex) tdpr value (hex) pg3..pg0 0 8000 8200 0 1 8400 8600 2 288008a004 3 8c00 8e00 6 4 9000 9200 8 5 9400 9600 a 698009a00c 7 9c00 9e00 e row 1 left row 11 free space row 12/scroll buffer 0.5k tdsram row 1 right row 11 free space row 12/scroll buffer 6k 2k 8k see figure 22 for address values 0.5k tdsram header resolution 0.5k bytes status row 0 status row 1 free space free space row attr. 100h
117/178 st92185b - on screen display (osd) on screen display (contd) 7.4.7 font mapping g0 is the basic character font. g1 is the mosaic font. it is not stored in rom but is implemented in hardware. in serial mode it is ad- dressed by a serial attribute (see figure 3 ). in par- allel mode it is accessed by bit 0 (css) of the par- allel shape attribute and bit 1 (us) for separated mosaic (see figure 4 ). g2 is a font of x/26 based + menu shared charac- ters. an extended menu character font available in par- allel mode. it is accessed via bit 0 (css) in the par- allel shape attribute (character set selection). the extended menu font is not accessible in serial mode. 7.4.8 font mapping modes there are two font mapping modes selected by the ncm bit in the ncsr register r245 (f5h) page 32: single g0 mode a set combining 83 characters from the g0 basic set plus 13 characters selected from 15 national character subsets. the national character sub- sets are selected by four bits (nc3:0) in the ncsr register r245 (f5h) page 32. triple g0 mode three 96-character character sets (g0-0, g0-1 and g0-2) for multi al- phabet applications. character set selection is done by four bits (nc1:0 or nc3:2) in the ncsr register r245 (f5h) page 32. C in serial mode (level 1), only 256 character codes are available using an 8-bit code. the character codes plus some serial attributes and some additional programmable options address 566 chars: 256 + 182 ns chars + 128 mosaics in single g0 mode. C in parallel mode (enhanced level 1), 512 char- acter codes are available using a 9-bit code. the character codes plus some serial and parallel at- tributes, and some additional programmable op- tions address 662 chars: 256 + 182 ns chars + 128 mosaic + 96 extended chars. in single g0 mode. display rom font entry: the user must define his own fonts for: C 278 characters: - 15 x 13 g0 national character subsets + 83 g0 character set or C 288 characters: 3 x 96-character character sets C 128 g2 based x/26 and menu characters C 96 extended menu characters table 21. triple g0 mode - font mapping rom address character code css font usage 000h to 01fh 0e0h to 0ffh 1 extended menu 020h to 07fh 020h to 07fh 0 (or serial mode) g0 set 0 080h to 0ffh 080h to 0ffh g2 + menu 100h to 15fh 020h to 07fh g0 set 1 160h to 1bfh 020h to 07fh g0 set 2 1c0h to 1ffh 0a0h to 0dfh 1 extended menu
118/178 st92185b - on screen display (osd) on screen display (contd) table 22. national character subset mapping (ordered by their g0 address) figure 78. font mapping 1st 2nd 3rd 4th 5th 6th 7th 23h 24h 40h 5bh 5ch 5dh 5eh 8th 9th 10th 11th 12th 13th 5fh 60h 7bh 7ch 7dh 7eh parallel mode (ps=x, css=0) serial attributes (32 codes) g2 based + menu (128 codes) g0 + optional national set 80 ff addresses char. codes (96 codes) 01f 7f 01f 7f80 ff serial attributes (32 codes) g2 based + menu (128 codes) g0 + optional national set 80 ff serial mode addresses char. codes (96 codes) g1* (32) g1* (32) *if serial attributes 19, 1a are used 01f3f 5f7f 01f 7f80 ff serial attributes (32 codes) extended menu characters (96 codes) 80 ff addresses char. codes g1 (32) g1 (32) 01f3f 5f 7f 100 11f 17f 19f 1ff parallel mode (ps=1, css=1) g0 (32) reserved (32) 180 9f
119/178 st92185b - on screen display (osd) on screen display (contd) table 23. single g0 mode - font mapping table 24. national character subsets rom address character code css font usage nc(3:0) 000h to 01fh 0e0h to 0ffh 1 extended menu 020h to 07fh 020h to 07fh 0 g0 + national character subset 0 (96 chars) 0000b 080h to 0ffh 080h to 0ffh g2 + menu (128 chars) 100h to 10ch (see table below) national character subset 1 (13 chars) 0001b 10dh to 119h (see table below) national character subset 2 (13 chars) 0010b 11ah to 126h (see table below) national character subset 3 (13 chars) 0011b 127h to 133h (see table below) national character subset 4 (13 chars) 0100b 134h to 140h (see table below) national character subset 5 (13 chars) 0101b 141h to 14dh (see table below) national character subset 6 (13 chars) 0110b 14eh to 15ah (see table below) national character subset 7 (13 chars) 0111b 15bh to 167h (see table below) national character subset 8 (13 chars) 1000b 168h to 174h (see table below) national character subset 9 (13 chars) 1001b 175h to 181h (see table below) national character subset 10 (13 chars) 1010b 182h to 18eh (see table below) national character subset 11 (13 chars) 1011b 18fh to 19bh (see table below) national character subset 12 (13 chars) 1100b 19ch to 1a8h (see table below) national character subset 13 (13 chars)(free for user) 1101b 1a9h to 1b5h (see table below) national character subset 14 (13 chars) (menu chars.) 1110b 1c0h to 1ffh 0a0h to 0dfh 1 extended menu 23 5c 5b 40 24 5d 5e 5f 60 7b 7c 7d 7e estonian 9 czech/slovak 3 english 0 french 1 german 4 italian 6 lettish/ 10 polish 8 portugese/ 5 rumanian 7 serbian/ 12 swedish/ 2 turkish 11 lithuanian spanish croatian/ slovenian finnish subset no. character code (hex) subset name (decimal)
120/178 st92185b - on screen display (osd) on screen display (contd) figure 79. pan-european font (east/west) character codes (hex.) figure 80. osd picture in parallel mode national character subset 0 menu g0_0 g2-menu extended menu extended char. national subsets 1..14d
121/178 st92185b - on screen display (osd) on screen display (contd) 7.4.9 register description horizontal blank register (hblankr) r240 - read/write register page: 32 reset value: 0000 0011 (03h) it controls the length of the horizontal blank which follows the horizontal sync pulse. bit 7:0 = hb[7:0] : the horizontal blank period is calculated with a pixel down counter loaded on each hsync by hb[7:0]. during this period, fb = 0 and (r, g, b) = black. thblank = [(hb7*128 + hb6*64 + hb5*32 + hb4*16 + hb3*8 + hb2*4 + hb1*2 + hb0) * tpix] horizontal position register (hposr) r241 - read/write register page: 32 reset value: 0000 0011 (03h) bit 7:0 = hp[7:0] : the horizontal start position is calculated with a pixel down-counter loaded on each hsync by hp[7:0]. the first character display starts when the counter turns to zero. hori delay= [(hp7*128 + hp6*64 + hp5*32 + hp4*16 + hp3*8 + hp2*4 + hp1*2 + hp0) * tpix] + thblank vertical position register (vposr) r242 - read/write register page: 32 reset value: 0000 0000 (00h) bit 7:6 = reserved, keep in reset state. bit 5:0 = vp[5:0]: the vertical start position is cal- culated with a line downcounter decremented on each hsync by vp[5:0]. the display of the first row begins when the counter turns to zero. vert delay = (vp5*32 + vp4*16 + vp3*8 + vp2*4 + vp1*2 + vp0) * tline (tline= 64 s) 70 hb7 hb6 hb5 hb4 hb3 hb2 hb1 hb0 70 hp7 hp6 hp5 hp4 hp3 hp2 hp1 hp0 70 0 0 vp5 vp4 vp3 vp2 vp1 vp0
122/178 st92185b - on screen display (osd) on screen display (contd) full screen color control register (fsccr) r243 - read/write register page: 32 reset value: 0000 0000 (00h) bit 7 = be : box enable, see table 11 . bit 6 = tio : text out/not in, see table 11 . bit 5 = mm : mixed mode, see table 11 . note: when flash and box attributes are decoded at the same time on the characters of a header (when be=1, mm=1, tio=1) the full screen over the characters is displayed as transparant. bit 4 = htc : half-tone/translucency control bit this bit allows the selection of tslu or ht as al- ternate function output. 0: tslu is selected as i/o pin alternate function 1: ht is selected as i/o pin alternate function bit 3:0 = fsc[3:0] : full screen color control bits : fsc[3:0]= (half-intensity, r, g, b) table of color values (hex) table 25. box mode/translucency configurations 70 be tio mm htc fsc3 fsc2 fsc1 fsc0 0 black 8 black 1 blue 9 dark blue 2 green a dark green 3 cyan b dark cyan 4 red c dark red 5 magenta d dark magenta 6 yellow e dark yellow 7 white f grey be tio mm if translucency is not used if translucency is used 0 x 0 solid background for all the display translucent background for all the display 0 x 1 transparent background for all the display transparent background for all the display 1 0 0 text inside box solid, text outside box blanked text inside box translucent, text outside box blanked 10 1 text inside box with solid background text out- side box with transparent background text inside box with translucent background text outside box with transparent background 11 0 text inside box not displayed, transparent back- ground. text outside box with solid background text inside box not displayed, transparent back- ground. text outside box with translucent back- ground 11 1 text inside box with transparent background. text outside box with solid background text inside box with transparent background. text outside box with translucent background
123/178 st92185b - on screen display (osd) on screen display (contd) header & status control register (hscr) r244 - read/write register page: 32 reset value: 0010 1010 (2ah) bit 7:6 = reserved. bit 5,3 = es[1:0] : enable status rows [1:0] dis- play control bits. if the bit is reset, the correspond- ing status row is filled with the full screen color; if the bit is set, the corresponding status row is dis- played (status row 1 is assumed to be the bottom one). bit 4,2 = ns[1:0] : serial/parallel mode status rows display control bits . if the corresponding bit is reset, the status row uses only serial attributes. if the corresponding bit is set, the status row uses parallel attributes (except size attributes). bit 1 = eh : enable header display control bit . if set, the header row is displayed; if reset, the header row is filled with the full screen color. bit 0 = nh : serial/parallel mode header display control bit. if the bit is reset, the header uses only serial attributes. if the bit is set, the header uses of parallel attributes. 70 0 0 es1 ns1 es0 ns0 eh nh
124/178 st92185b - on screen display (osd) on screen display (contd) national character set register (ncsr) r245 - read/write register page: 32 reset value: 0000 0000 (00h) the register bit values are sampled and then acti- vated only at each field start (on vsync pulse). bit 7 = tsle: translucency/half-tone output en- able bit. 0: translucency/half-tone signal disabled 1: translucency/half-tone is enabled. translu- cency or half-tone realtime control signal is routed in the tslu/ht pin (depending on the htc bit in the fsccr register). note: translucent display depends also on the be, tio and mm bits, see table 11 . bit 6 = reserved. bit 5 = swe : g0 switch enable control bit . in case of a multiple g0 alphabet configuration (ncm=1), this bit allows to switch from a first to a second predefined g0 alphabet, using a single se- rial attribute (1bh). in case of a single g0 alphabet configuration (ncm=0), the swe bit will have no effect. if swe is reset, the used g0 alphabet is pointed through nc[1:0]. if swe is set, the used g0 alphabet is pointed through nc[3:2] and nc[1:0] toggled by 1bh serial attribute. bit 4 = ncm : national character mode control bit. this bit reconfigures a part of the font set as defin- ing: C either a single g0 alphabet with up to 15 national sub-sets, C or 3 different g0 alphabets. if ncm is reset, a single g0 alphabet configuration is activated and the 15 national sub-sets are se- lected through the nc[3:0] bits. if ncm is set, a triple g0 alphabet configuration is activated, the selection of the g0 set used for the display is done through either nc[3:2] or nc[1:0] bits, depending upon the swe control bit and the serial attribute 1bh values. bit 3:0 = nc [ 3:0 ]: national character set selec- tion . if the ncm bit is reset, these bits define which na- tional sub-set has to be used to complete the basic currently used g0 alphabet set. if the ncm is set, these bits define which g0 is used. figure 81. national characters selection 70 tsle 0 swe ncm nc3 nc2 nc1 nc0 ncm swe nc[3:0] g0-0 g0-1 g0-2 g0-0 g0-1 g0-2 g0-0 g0-1 g0-2 serial attr. 1bh nc[1:0] nc[3:2] nc[1:0] toggle ns0 ns1 ns14 15 national char. sets 3 g0 sets 0 0 1 1
125/178 st92185b - on screen display (osd) on screen display (contd) cursor horizontal position register (chposr) r246 - read/write register page: 32 reset value: 0000 0000 (00h) bit 7 = reserved. bit 6:0 = chp[6:0] : cursor horizontal position . the cursor is positioned by character. chp= 0 points to the first character chp= 39d points to the end of the row (single page display) chp= 79d points to the last character in the row (double page display) cursor vertical position register (cvposr) r247 - read/write register page: 32 reset value: 0000 0000 (00h) bit 7 = fon : "flash on" flag bit. the fon bit remains at "0" during 32 consecutive tv fields followed by a "1" state during the 16 next tv fields. this flag provides a 1hz time reference for an easy software control of all flashing effects (assuming a 50 hz tv signal, the fon total period will be 0.96 seconds). this bit is read only. trying to write any value will have no effect. bit 6:5 = cm[1:0]: cursor mode control bits . bit 4:0 = cvp[4:0] : cursor vertical position . the cursor is positioned by row. the cursor is al- ways single size. cvp= 0 locates the cursor on the header row cvp= 25d locates the cursor on the last status row. 70 0 chp6 chp5 chp4 chp3 chp2 chp1 chp0 70 fon cm1 cm0 cvp4 cvp3 cvp2 cvp1 cvp0 cm1 cm0 cursor mode 0 0 cursor disable 01 static cursor (inverted foreground & invert- ed background colours) 10 flash cursor (flash from current to inverted colours & vice versa) 11 cursor done with underline (use of current foreground color)
126/178 st92185b - on screen display (osd) on screen display (contd) scrolling control low register (sclr) r248 - read/write register page: 32 reset value: 0000 0000 (00h) bit 7 = sce : scrolling enable before enabling scrolling, the scrolling area must be defined by the frs[4:0] and lrs[4:0] bits. the scrolling direction is defined by the up/d bit. 0: disable scrolling 1: enable scrolling bit 6 = fsc : freeze scrolling note: the 2 control bits sce and fsc must be set to "1" before enabling the global double height (see the dh bit in the schr register). bit 5 = ss : scrolling speed control bit. 0: the display is shifted by 2 tv lines at each tv frame (i.e. after 2 vertical sync pulses). 1: the display is shifted by 4 tv lines at each tv frame. bit 4:0 = frs[4:0] : these bits define the upper- most row value to be scrolled (rows are num- bered from 1 to 23). in case of global double height mode programming, frs[4:0] must mandatorily be equal to 00000. table 26. scrolling control bits 70 sce fsc ss frs4 frs3 frs2 frs1 frs0 dh sce fsc up/d frs[4:0] lrs[4:0] meaning 0 0 x x x x no global double height, no scrolling 01x 1 x x no global double height, scroll up 0 x x no global double height, scroll down 10x 1 0 x global double height, no scrolling, display top half 0 0 x global double height, no scrolling, display bottom half
127/178 st92185b - on screen display (osd) on screen display (contd) scrolling control high register (schr) r249 - read/write register page: 32 reset value: 0000 0000b (00h) bit 7 = dh : global double height control bit . this bit must only be used in page mode. when dh is set, the display is turned in double height in- cluding the header, excluding the vertical offset before the display area. the status rows are not affected by the dh bit and they remain in normal height. depending on the value of the up/d con- trol bit, when dh is set, the first or second half of the page is displayed in double height. this bit as- sumes a zooming function. notes: C in global double height, when the top half page is displayed, if row 11 has a double height at- tribute, the first status row is corrupted. to avoid this effect, save row 11, remove the serial double height attribute from this row and display the up- per part of the page. then, before displaying the lower part of the page, restore the serial dh at- tribute in row 11. C when the bottom half page is displayed, if row 23 has a double height attribute, the first status row is not displayed. to avoid this effect remove the serial double height attribute from row 23. bit 6 = eer : end of extra row flag bit. this bit is forced to "1" by hardware when the last line of the extra row is displayed in case of scroll- ing in normal height. this bit is read only. in global double height, the eer bit is set to "1" each time the last line of a new displayed row ap- pears. bit 5 = up/d : scrolling up/down this bit has two functions: to control the scrolling direction and to select the half part of the page in global double height display. scrolling direction: 0: top-down shift 1: bottom-up shift half-page selection: when dh is set, if up/d is set, the upper half of the page is displayed (i.e. header and the page rows 1 to 11). when dh is set, if up/d is reset, the lower half of the page is displayed (i.e. rows 12 to 23 and the status rows). the up/d control bit must be defined before set- ting the global height (dh bit); changing up/d af- ter dh is set, will not change the already selected half page. bit 4:0 = lrs[4:0] : last row to be scrolled (1 to 23). in case of scrolling in global double height, the last row must be equal to 0x 10111 to display the status row in the two half pages. 70 dh eer up/d lrs4 lrs3 lrs2 lrs1 lrs0
128/178 st92185b - on screen display (osd) on screen display (contd) figure 82. memory management for scrolling window row a row b row c row a row b row c row d row b row c row d row a row b row c row d row a row b row c row a row b row c row d row a row b row c row d row a row b row c row d row a row b row c row a row b row c row d row b row c row d row b row c row d row e normal height t0 3 rows to be scrolled t + 5 vsync t + 10 vsync t + 15 vsync eer=0 eer=0 eer=1 eer=0 row a row b row c row d row b row c row d row e tdsram content display area row 24 row 24 tdsram content new a = first row to scroll c= last row to scroll e= extra row freeze off after 5 vsync freeze on after 5 vsync new tdsram address after eer=1
129/178 st92185b - on screen display (osd) on screen display (contd) display control mode 0 register (dcm0r) r250 - read/write register page: 32 reset value: 0000 0000 (00h) bit 7 = de : display enable control bit . if de is reset, no display will be performed. if de is set, a display will be done as defined through the various control bits. bit 6 = ste : semi-transparent enable bit . this bit is active only in single page display mode. while the display is disabled, the horizontal and vertical sequencers are forced in their reset state and the rgb & fb dacs are not off (still present- ing on-chip resistors to ground). note: this mode shows a visible grid on the screen. bit 5 = fre : fringe enable control bit . if this bit is set, and the swe bit is reset (refer to the national character set register description) the serial attribute 1bh has a fringe toggle func- tion. bit 4 = ce : conceal enable control bit . 0: reveal any text defined as concealed by serial attributes (default) 1: conceal any text defined as concealed by serial attributes bit 3 = gfr : global fringe enable control bit. if this bit is set, the whole display is in fringe mode (except if a double page display mode is pro- grammed). bit 2 = gre : global rounding enable control bit . if this bit is set, the whole display is in rounding mode (except if a double page display mode is programmed). bit 1 = sf : screen format control bit . 0: configures the display for 4/3 tv screen format. 1: a fixed offset of 128 pixel clock periods is added before any character is displayed; the full screen color attribute is used while the offset is running. the sf bit intended for displaying on 16/9 tv screen format tubes, the display picture will be re- centered. bit 0 = s/d: single or double page control bit. 0: a single page is displayed on screen (i.e. 40- character width). 1: a set of two pages is displayed contiguously (i.e. 80-character width). note: in 80 characters per row and in full page mode, line 25 of each field is displayed as a transparant line (as this line is not in the visible part of the screen, this should not present a limita- tion). programming a double page display will automat- ically mask the fringe, rounding and parallel mode control bits. their register values are not changed and they will automatically recover their initial effect if the display is switched back in a sin- gle page mode. 70 de ste fre ce gfr gre sf s/d fre swe 1bh serial attribute acts as: 0 0 no action 0 1 g0 toggle 1 0 fringe toggle 1 1 g0 toggle
130/178 st92185b - on screen display (osd) on screen display (contd) display control mode 1 register (dcm1r) r251 - read/write register page: 32 reset value: 0000 0000 (00h) bit 7:4 = reserved bits, keep in reset state. bit 3 = extf : external font. only when the emulator is used, this bit selects the font memory containing a user-defined osd font. in normal user application, this bit has no effect. 0: internal font memory of the emulator chip. 1: external font ram of the emulator board. bit 2 = fbl : fast blanking active level control bit. the fbl bit must be reset if the on-screen display is done while the fb output is low. the fbl bit must be set if the on-screen display is done while the fb output is high. this bit also controls the tslu af output polarity with the same rule as for fb. bit 1 = pm : line mode control bit . if pm is reset, the display is working in full page mode, i.e. the screen is composed of one header, 23 text rows plus 2 status rows. if pm is set, the display works in line mode. line mode allows up to 12 rows to be displayed anywhere on the screen. the row attribute (see tdsram mapping) contains the row numbers on the screen. the byte position of the row attribute conrresponds to the row in the tdsram. for ex- ample, if the 3rd byte of the row attribute contains 6, the 3rd row in tdsram will be displayed as the 6th row on the screen. bit 0 = spm : serial/parallel mode control bit . if the spm bit is reset, the display is done in serial mode, i.e. a character or attribute is coded with a single byte. if the spm bit is set, the display is done in parallel mode, i.e. a character or an at- tribute is coded on two bytes. tdsram pointer register (tdpr) r252 - read/write register page: 32 reset value: 0000 0000 (00h) bit 7:4 = hs[3:0]: location of the current header and status rows in the tdsram. bit 3:0 = pg[3:0] : location of the current page content (rows 1 to 23) in the tdsram. for more details, refer to section . the hs[3:0] and pg[3:0] bits described by the r246 and r247 registers in page 32. display loca- tions, head/stat location, page location, are phys- ically the same: these sets of address bits can be modified through two different programming ac- cesses. 70 0000extffblpmspm 70 hs3 hs2 hs1 hs0 pg3 pg2 pg1 pg0
131/178 st92185b - on screen display (osd) on screen display (contd) display enable 0 control register (de0r) r253 -read/write register page: 32 reset value: 1111 1111 (ffh) bit 7:0 = r[8:1] : row display enable control bit . when the ri bit is set (reset value), the corre- sponding row (with row in the page, numbered from 1 to 23) will be displayed. when the ri bit is reset, the full screen color is displayed. display enable 1 control register (de1r) r254 -read/write register page: 32 reset value: 1111 1111 (ffh) bit 7:0 = r[16:9] : row display enable control bit . when the ri bit is set (reset value), the corre- sponding row (with row in the page, numbered from 1 to 23) will be displayed. when the ri bit is reset, the full screen color is displayed. display enable 2 control register (de2r) r255 -read/write register page: 32 reset value: x111 1111 (xfh) bit 7 = reserved . bit 6:0 = r[23:17] : row display enable control bit . when the ri bit is set (reset value), the corre- sponding row (with row in the page, numbered from 1 to 23) will be displayed. when the ri bit is reset, the full screen color is displayed. 70 r8 r7 r6 r5 r4 r3 r2 r1 70 r16 r15 r14 r13 r12 r11 r10 r9 70 x r23 r22 r21 r20 r19 r18 r17
132/178 st92185b - on screen display (osd) on screen display (contd) default color register (dcr) r240 - read/write register page: 33 reset value: 0111 0000 (70h) bit 7:4 = dfg[3:0] : default foreground color. dfg[3:0] = (half-intensity, r, g, b) bit 3:0 = dbg[3:0] : default background color dbg[3:0] = (half-intensity, r, g, b) table of color values (hex) cursor absolute vertical position register (capvr) r241 - read/write register page: 33 reset value: 0000 0000 (00h) bit 7:5 = reserved, keep in reset state. bit 4:0 = acp[4:0]: absolute vertical position of the cursor in case of double height or scrolling. tdsram page pointer register (tdppr) r246 - read/write register page: 33 reset value: xxx0 0000 (x0h) bit 7:4 = reserved, keep in reset state. bit 3:0 = pg[3:0] : page pointer location of the current page content (rows 1 to 23) in the tdsram. for more details, refer to the dis- play memory mapping section . tdsram header/status pointer regis- ter (tdhspr) r247 - read/write register page: 33 reset value: xxx0 0000 (x0h) bit 7:4 = reserved, keep in reset state. bit 3:0 = hs[3:0] : header/status rows pointer location of the current header and status rows in the tdsram. for more details, refer to the dis- play memory mapping paragraph section . 70 dfg3 dfg2 dfg1 dfg0 dbg3 dbg2 dbg1 dbg0 0 black 8 black 1 blue 9 dark blue 2 green a dark green 3 cyan b dark cyan 4 red c dark red 5 magenta d dark magenta 6 yellow e dark yellow 7 white f grey 70 0 0 0 acp4 acp3 acp2 acp1 acp0 70 x x x 0 pg3 pg2 pg1 pg0 70 x x x 0 hs3 hs2 hs1 hs0
133/178 st92185b - on screen display (osd) 7.4.10 application software examples before starting an osd display, it is very important to start all the internal clock/timings to understand the software routines given below, make a thorough study of the chapters on the reset and clock control unit (rccu) and the tdsram interface. initialization of the internal clock ;========================================================================= ; main clock init ;========================================================================= clocks:: ;--------- cpu main clock ------------ ; c k m a i n provided by the freq. multplier spp #tccr_pg; timings & clock controller registers page ; page 39 or 27 ld mccr,#0x05; program the frequency multiplier down ; counter in the feed-back loop (253 =fd) ; freq=(5+1)*2 =12mhz ; freq=(7+1)*2 =16mhz ; freq=(8+1)*2 =18mhz ld mccr,#0x85; enable the freq. multiplier srp #bk20 ldw rr0,#0x2fff; time_stab1: ; for frequency multiplier stabilization decw rr0; change cpu source clock & wait clock stabilization cpw rr0,#0x00; jxnz time_stab1; ld mccr,#0xc5 ; select the freq. multiplier as main clock pop ppr ;========================================================================= ; synchro start ;========================================================================= spp #sycr_pg ; set page pointer to page 23h or 35 decimal ld csyctr,#000h; r243, hsync and vsync from deflection part (external) ld csysur,#0c4h; r242 sync controller set-up register ; standard mode, positive polarity of hsync & vsync ; delay on hsync/vsync hsf(3:0)=9 ;========================================================================= ; display pixel clock ;========================================================================= ; spp #tccr_pg; timings & clock controller registers page ; set page pointer to page 39 decimal ld skccr, #0x09; fe, skew clock control register ; program the frequency multiplier down ; counter in the feed-back loop
134/178 st92185b - on screen display (osd) ; dot_freq= 4mhz(4+1)=20mhz (4/3) ; dot_freq= 4mhz(5+1)=24mhz (16/9) ; divide by 2 ld skccr, #0x89; enable the freq. multiplier srp #bk20 ldw rr0,#0x0fff; time_stab2: ; for frequency multiplier stabilization decw rr0; skew clock stabilization cpw rr0,#0x00 ; jxnz time_stab2; ld pxccr,#0x80;(pxccr) start pixel line pll spp #tdsr_pg2; page 26h, tdsram controller registers third page srp #000h ld config, #003h; fc, ram interface configuration register ; enable display and dram access ;======================================================================= initialization of the osd in serial mode ;======================================================================= ; init display routine ;======================================================================= init:: ;-----------display position & black reference spp #dmp1_pg; page 020h display memory map registers page ld hblankr,#0x45; hblankr register [7: 0]; reset=03 ; important delay for black reference on rgb cathod ld hposr,#0x35; hposr register [7:0]; reset=03 ld vposr,#0x10; vposr register [5:0]; reset=00 ;----------------- spp #dmp1_pg; page 020h display memory map registers page ; f3, full screen color register ld fsccr, #0x01 ; no subtitle mode ; be, box enable ; tio, text in/out ; mm, mixed mode ; fsc[3:0]=half blue full screen ld hscr, #03fh; bit5, 4, 3, 2, 1, 0 ; es1 , ns1, es0, ns0, eh, nh ; 0x3f > set header and status in level 1+ ; (parallel) ; 0x2a > set header and status in level 1 ; f5, national characters register ld nc, #010h; swe, ncm, nc[3:0] ;------- scrolling init ---------- spp #dmp1_pg; page 020h display memory map registers page
135/178 st92185b - on screen display (osd) ; f8, scrolling control line register ld sclr ,#000h ; sce, fsc, ss, firstrowscro[4:0] ; f9, scrolling control horizontal register ld schr ,#02fh ; dh, er, up/d, lastrowscro[4:0] ;------- cursor position ; f8, scrolling control line register ld sclr ,#000h ; sce, fsc, ss, firstrowscro[4:0] ; f9, scrolling control horizontal register ld schr ,#02fh ; dh, er, up/d, lastrowscro[4:0] ; f6, cursor horizontal position register ld chposr , #005h; cursor hpos [6:0] ; f7, cursor vertical position register ld cvposr , #000h; fon, cm[1:0], cursor vpos[4:0] ;------- control ; fa, control mode 0 register ld dcm0r,#0a0h; de, ste, fre, ce, gfr, gre, sf=4/3, s/d=40 ; display enable ; solid mode ; toggle fringe enable ld dcm1r,#0x04; register 251 (fbh) control mode 1 register ; dat[6:4]/bits 7,6,5 & tdr/bit4 ; fnex=0, on-chip font ; fbl=1 fastblanking active high ; pm =0 full page mode ; spm =0 serial mode ;--------dram location: header/status rows, current display ; fc, dram location register ld tdpr, #080h; hs[3:0], ad[3:0] ; for header bit12=1 ;------- foreground/background spp #dmp2_pg; page 021h display memory map registers page ld dc, #07fh ; reg. f0h, dfg [3:0], dbg [3:0] ; fg full white ; bg grey (half white) ;----------------------------- spp #dmp1_pg; page 020h display memory map registers page ld de0r, #0ffh; rowen [8:1] ld de1r, #0ffh; rowen [16:9] ld de2r, #0ffh; rowen [23:17] ret =======================================================================
136/178 st92185b - sync controller 7.5 sync controller the sync controller receives horizontal / vertical sync information coming from the chassis. the vsync and hsync inputs use schmitt triggers to guarantee sufficient noise rejection. the sync controller unit provides the h internal sync signal to the display skew corrector, which rephases the pixel clock. it provides also the h and v internal sync signals to the tdsram controller to perform correct tv line counting, thus generating the necessary time windows for a proper tdsram access real time sharing by the display controller and the cpu (for more details refer to the tdsram controller chap- ter). field information is also available for the dis- play controller. the sync controller unit also generates two in- terrupt sources corresponding respectively the tv field start and to the end of vbi event (vbi stands for vertical blank interval). the sync controller implements also a compos- ite sync signal generator which provides a com- posite sync output signal (called cso) available through an i/o port alternate function. figure 83. sync controller block diagram n hout 1 0 1 0 pgmble delay hsf(3:0) line counter eofvbi interrupt vout hflg pulse shaper eofvbi fldst fldev mod0 mod1 hsf(3:0) vpol hpol sccs0 register sccs1r register fsten vsep vdly vbien skew corrector hint field detect. fldev vout vout fldst interrupt pulse shaper (to display, etc.) (to display, etc.) vsync vpol vsep vertical sync extr. vdly hsync hpol csync hpls cso_af vpol field mod1 mod0 4 mhz (from sync ext.) mod1 hpls equalization pulse vertical pulse generator & line sequencer (mod0+mod1)*vsep vertical controller mod0 internal h generator (64 s) composite sync. generator vcso vr02092a
137/178 st92185b - sync controller sync controller (contd) 7.5.1 h/v polarity control two control bits manage the h/v polarities. hpol (sccs0r.6) manages the hsync polarity (a pos- itive polarity assumes the leading edge is the ris- ing one). vpol (sccs0r.7) controls the vsync polarity. 7.5.2 field detection field detection is necessary information for the display controller for fringe and rounding features. to determine correctly the field in case of using separate h and v input signals, it is necessary to provide an internal compensation of the hardware delay generated on vsync (vsync is generally issued by integrating the equalization pulses). therefore the vsync leading edge is compared to the leading edge of an internally delayed hsync. the delay applied to hsync is software program- mable through the sccs0r (3:0) bits (from 0 to 63 s). it must be calculated by the user as being the time constant (modulo 64 s) used to extract vsync by the other components of the chassis. 7.5.3 interrupt generation the sync controller unit can provide two different interrupts to the st9+ core. the first interrupt ap- pears at each beginning of field upon detection of the vertical sync pulse coming from the deflection circuitry (i.e. from vsync); it is called the field start interrupt. a flag is associated to this inter- rupt, called fldst (sccs1r.6). this flag is set to 1 by hardware when the vertical sync pulse appears. it must be cleared by software. the second interrupt appears at the end of each vertical blank interval. it is generated at the begin- ning of the line 25 counted from the deflection cir- cuitry (i.e. from vsync); and is called the end of vbi interrupt. a flag is associated to this interrupt, called eofvbi (sccs1r.7). this flag is set to 1 by hardware when the line 25 starts. it must be cleared by software. these two interrupts eofvbi and fldst are re- spectively attached to the int4 and int5 external interrupt inputs of the st9+ core. the leading edges of the 2 interrupt requests are the falling ones. (for more details, refer to the interrupts chapter). 7.5.4 sync controller working modes different working modes are available fully control- led by software. the first two working modes assume that tv de- flection sync signals are available and stable. the last two modes assume that no tv signal is available. the chip works in a free-running mode providing standard tv sync signals based on the main internal 4 mhz clock. switching from one mode to any other is done un- der full software control, through the programming of two control bits called as mod1 and mod0. these control bits are described in the sccs1r register 7.5.4.1 standard sync input mode this mode is accessed when both mod1 and mod0 bits are reset. in this mode, the p receives the chassis synchro through two separate inputs. these are vsync and hsync. it also assumes the vsep (sccs0r.5) is reset.
138/178 st92185b - sync controller sync controller (contd) 7.5.4.2 composite sync input mode this mode is very similar to the standard sync in- put mode described above. it is also accessed when both mod1 and mod0 bits are reset. in composite sync mode, a single csync/ hsync input pin is used to enter both the horizon- tal and vertical sync pulses (vsep control bit is set to 1). in this mode, the vsync pin must be tied to vss on the application board to prevent a floating cmos input configuration. the csync signal characteristics are assumed to perfectly respect the stv2160 txtout pin spec- ification which is reviewed in figure 84 & figure 85 . the vertical sync signal is extracted from the csync signal by the mean of an up/down coun- ter used as a digital integrator. the counter works in up mode during the sync pulses. two time constants can be programmed using the vdly control bit (refer to the register description). the smallest one corresponds to 16s; the second one being 32s. figure 84. stv2160 txtout timings n 1st tv field 2nd tv field txtout txtout 623 624 625 12 345 6 311 312 313 314 315 316 317 318 319 8s 8s 58s 38s 8s 8s 8s 58s 6s 8s vr02092b
139/178 st92185b - sync controller sync controller (contd) 7.5.4.3 free-running monitor sync mode this mode is accessed when the mod1 bit is set. in this mode, the chassis hsync and vsync sig- nals are not used. they are replaced by the sync signals which are fully crystal based (use of the in- ternal main 4 mhz clock). two free-running monitor modes are available: when the mod0 bit is reset the composite sync output (cso) is generated for a 60hz format; when the mod0 bit is set to 1 the composite sync output (cso) is generated for a 50hz format. for both formats, the tv line period is 64s. the composite sync alternate function output (cso) can be activated or disabled under control of the vsep bit. in free-running monitor sync mode, the vpol control bit is used to control whether an interlaced or non-interlaced tv context must be generated. when the non-interlaced context is programmed, only the 1st tv field configuration is generated. figure 85. even/odd field timings n d1 1st tv field 2nd tv field 623 624 625 12 345 6 311 312 313 314 315 316 317 318 319 622 d1 d2 523 524 525 12 345 6 522 (50 hz mode) (60 hz mode) 310 d1 261 262 263 264 265 266 267 268 269 260 (50 hz mode) (60 hz mode) d2 d2 = 2.25 s d1 = 4.75 s vr02092c
140/178 st92185b - sync controller sync controller (contd) 7.5.5 register description sync controller control and status register 0 (sccs0r) r242 - read/write register page: 35 reset value: 0000 0000 (00h) bit 7= vpol . vsync polarity when mod[1:0] are reset, this bit configures the polarity of the vsync input. 0: negative polarity (leading edge is falling edge) 1: positive polarity (leading edge is rising edge) for other cases: bit 6= hpol . hsync/csync polarity . 0: negative polarity (leading edge is falling edge) 1: positive polarity (leading edge is rising edge) bit 5= vsep . separate sync when mod[1:0] are reset: 0: the standard mode using two inputs (vsync and hsync) is activated. 1: the composite sync mode is activated; the hsync/csync input will be used to get both h and v signals. for other cases: bit 4= vdly . vertical delay control bit . this bit is active only if the composite sync mode is enabled. the selection of this bit can effect noise margin (longer delay is better) and the field detection. 0: vertical is generated after detecting a pulse greater than 16s 1: vertical is generated after detecting a pulse greater than 32s bit 3:0= hsf . horizontal shift for field detection . these 4 bits program the delay, in steps of 4s, applied to the hsync pulse in order to properly determine the field information by comparison with vsync. this value is a chassis constant depend- ing upon the way the separate h/v signals are generated. 0 vpol hpol vsep vdly hsf3 hsf2 hsf1 hsf0 mod1 mod0 vpol 0 0 x vsync polarity control x 1 0 interlaced x 1 1 non-interlaced 1 x 0 interlaced 1 x 1 non-interlaced mod1 mod0 vsep cso alternate function 0 0 x disabled x 1 0 disabled x 1 1 enabled 1 x 0 disabled 1 x 1 enabled
141/178 st92185b - sync controller sync controller (contd) sync controller control and status register 1 (sccs1r) r243 - read/write register page: 35 reset value: 0000 0000 (00h) bit 7= eofvbi: end of vbi flag . this bit is set to 1 by hardware at the beginning of the line 25 of the current field, when the end of vbi interrupt request is sent to the core. the eofvbi flag must be reset by software before the end of the current field. bit 6= fldst: field start flag . this bit is set to 1 by hardware on the leading edge of the vertical sync pulse when the field start interrupt request is forwarded to the core. the fldst flag must be reset by software before the end of the current field. bit 5= fldev: field even flag . this bit is read-only. it indicates which field is cur- rently running; 0: first field is running 1: second field is running bit 4= hflg: horizontal sync flag . this bit is read-only. it just copies the horizontal sync transient information issued by the horizontal pulse shape unit. the bit is read at 1 at during each h sync pulse and lasts to 1 up to 4 s. bit 3= fsten: field start interrupt enable . 0: the fldst interrupt is disabled and the exter- nal interrupt pin becomes the interrupt input. 1: the fldst interrupt is enabled and the inter- rupt from the external pin is disabled. bit 2= vbien: vbi interrupt enable . 0: the eofvbi interrupt is disabled and the exter- nal interrupt pin becomes the interrupt input. 1: the eofvbi interrupt is enabled and the inter- rupt from the external pin is disabled. bit 1:0= mod[1:0]: n 70 eofvbi fldst fldev hflg fsten vbien mod1 mod0 mod1 mod0 h & v sync sources cso cso generator 00 chassis sync pulses no - 0 1 reserved reserved 10 from xtal (60 hz) yes on-chip timing genera- tor; free-running 11 from xtal (50 hz) yes on-chip timing genera- tor; free-running
142/178 st92185b - serial peripheral interface (spi) 7.6 serial peripheral interface (spi) 7.6.1 introduction the serial peripheral interface (spi) is a general purpose on-chip shift register peripheral. it allows communication with external peripherals via an spi protocol bus. in addition, special operating modes allow re- duced software overhead when implementing i 2 c- bus and im-bus communication standards. the spi uses up to 3 pins: serial data in (sdi), serial data out (sdo) and synchronous serial clock (sck). additional i/o pins may act as device selects or im-bus address identifier signals. the main features are: n full duplex synchronous transfer if 3 i/o pins are used n master operation only n 4 programmable bit rates n programmable clock polarity and phase n busy flag n end of transmission interrupt n additional hardware to facilitate more complex protocols 7.6.2 device-specific options depending on the st9 variant and package type, the spi interface signals may not be connected to separate external pins. refer to the peripheral configuration chapter for the device pin-out. figure 86. block diagram n read buffer serial peripheral interface data register ( spidr ) polarity phase baud rate multiplexer st9 interrupt transmission end of spen bms arb busy cpol cpha spr1 spr0 data bus r254 intclk serial peripheral control register ( spicr ) r253 sdo sdi sck/int2 vr000347 10 int2 internal serial clock to mspi control logic i n t 2 intb0 * * common for transmit and receive
143/178 st92185b - serial peripheral interface (spi) serial peripheral interface (contd) 7.6.3 functional description the spi, when enabled, receives input data from the internal data bus to the spi data register (spidr). a serial clock (sck) is generated by controlling through software two bits in the spi control register (spicr). the data is parallel loaded into the 8 bit shift register during a write cy- cle. this is shifted out serially via the sdo pin, msb first, to the slave device, which responds by sending its data to the master device via the sdi pin. this implies full duplex transmission if 3 i/o pins are used with both the data-out and data-in synchronized with the same clock signal, sck. thus the transmitted byte is replaced by the re- ceived byte, eliminating the need for separate tx empty and rx full status bits. when the shift register is loaded, data is parallel transferred to the read buffer and becomes availa- ble to the cpu during a subsequent read cycle. the spi requires three i/o port pins: sck serial clock signal sdo serial data out sdi serial data in an additional i/o port output bit may be used as a slave chip select signal. data and clock pins i2c bus protocol are open-drain to allow arbitration and multiplexing. figure 2 below shows a typical spi network. figure 87. a typical spi network n 7.6.3.1 input signal description serial data in (sdi) data is transferred serially from a slave to a mas- ter on this line, most significant bit first. in an s- bus/i 2 c-bus configuration, the sdi line senses the value forced on the data line (by sdo or by an- other peripheral connected to the s-bus/i 2 c-bus). 7.6.3.2 output signal description serial data out (sdo) the sdo pin is configured as an output for the master device. this is obtained by programming the corresponding i/o pin as an output alternate function. data is transferred serially from a master to a slave on sdo, most significant bit first. the master device always allows data to be applied on the sdo line one half cycle before the clock edge, in order to latch the data for the slave device. the sdo pin is forced to high impedance when the spi is disabled. during an s-bus or i 2 c-bus protocol, when arbi- tration is lost, sdo is set to one (thus not driving the line, as sdo is configured as an open drain). master serial clock (sck) the master device uses sck to latch the incoming data on the sdi line. this pin is forced to a high im- pedance state when spi is disabled (spen, spicr.7 = 0), in order to avoid clock contention from different masters in a multi-master system. the master device generates the sck clock from intclk. the sck clock is used to synchronize data transfer, both in to and out of the device, through its sdi and sdo pins. the sck clock type, and its relationship with data is controlled by the cpol (clock polarity) and cpha (clock phase) bits in the serial peripheral control regis- ter (spicr). this input is provided with a digital fil- ter which eliminates spikes lasting less than one intclk period. two bits, spr1 and spr0, in the serial peripheral control register (spicr), select the clock rate. four frequencies can be selected, two in the high frequency range (mostly used with the spi proto- col) and two in the medium frequency range (mostly used with more complex protocols).
144/178 st92185b - serial peripheral interface (spi) serial peripheral interface (contd) figure 88. spi i/o pins n 7.6.4 interrupt structure the spi peripheral is associated with external in- terrupt channel b0 (pin int2). multiplexing be- tween the external pin and the spi internal source is controlled by the spen and bms bits, as shown in table 1 interrupt configuration . the two possible spi interrupt sources are: C end of transmission (after each byte). C s-bus/i 2 c-bus start or stop condition. care should be taken when toggling the spen and/or bms bits from the 0,0 condition. before changing the interrupt source from the external pin to the internal function, the b0 interrupt channel should be masked. eimr.2 (external interrupt mask register, bit 2, imbo) and eipr.2 (external interrupt pending register bit 2, imp0) should be 0 before changing the source. this sequence of events is to avoid the generating and reading of spurious interrupts. a delay instruction lasting at least 4 clock cycles (e.g. 2 nops) should be inserted between the spen toggle instruction and the interrupt pending bit reset instruction. the int2 input function is always mapped togeth- er with the sck input function, to allow start/stop bit detection when using s-bus/i 2 c-bus protocols. a start condition occurs when sdi goes from 1 to 0 and sck is 1. the stop condition occurs when sdi goes from 0 to 1 and sck is 1. for both stop and start conditions, spen = 0 and bms = 1. table 27. interrupt configuration spi data bus port latch sdi sck int2 sdo sck sdo sdi int2 bit port latch bit port latch bit spen bms interrupt source 0 0 external channel int2 0 1 s-bus/i 2 c bus start or stop condition 1 x end of a byte transmission
145/178 st92185b - serial peripheral interface (spi) serial peripheral interface (contd) 7.6.5 working with other protocols the spi peripheral offers the following facilities for operation with s-bus/i 2 c-bus and im-bus proto- cols: n interrupt request on start/stop detection n hardware clock synchronisation n arbitration lost flag with an automatic set of data line note that the i/o bit associated with the spi should be returned to a defined state as a normal i/o pin before changing the spi protocol. the following paragraphs provide information on how to manage these protocols. 7.6.6 i 2 c-bus interface the i 2 c-bus is a two-wire bidirectional data-bus, the two lines being sda (serial data) and scl (serial clock). both are open drain lines, to allow arbitration. as shown in figure 5 , data is toggled with clock low. an i2c bus start condition is the transition on sdi from 1 to 0 with the sck held high. in a stop condition, the sck is also high and the transition on sdi is from 0 to 1. during both of these conditions, if spen = 0 and bms = 1 then an interrupt request is performed. each transmission consists of nine clock pulses (scl line). the first 8 pulses transmit the byte (msb first), the ninth pulse is used by the receiver to acknowledge. figure 89. s-bus / i 2 c-bus peripheral compatibility without s-bus chip select
146/178 st92185b - serial peripheral interface (spi) serial peripheral interface (contd) table 28. typical i 2 c-bus sequences figure 90. spi data and clock timing (for i2c protocol) n phase software hardware notes initialize spicr.cpol, cpha = 0, 0 spicr.spen = 0 spicr.bms = 1 sck pin set as af output sdi pin set as input set sdo port bit to 1 sck, sdo in hi-z scl, sda = 1, 1 set polarity and phase spi disable start/stop interrupt enable start sdo pin set as output open drain set sdo port bit to 0 sda = 0, scl = 1 interrupt request start condition receiver start detection transmission spicr.spen = 1 sdo pin as alternate func- tion output load data into spidr scl = 0 start transmission interrupt request at end of byte transmission managed by interrupt rou- tine load ffh when receiv- ing end of transmission detection acknowledge spicr.spen = 0 poll sda line set sda line spicr.spen = 1 sck, sdo in hi-z scl, sda = 1 scl = 0 spi disable only if transmitting only if receiving only if transmitting stop sdo pin set as output open drain spicr.spen = 0 set sdo port bit to 1 sda = 1 interrupt request stop condition sda scl start condition 12 8 9 1st byte ack clock pulse for acknowledgement driven by software 12 89 driven by sw for acknowledgement clock pulse condition stop ack n byte th vr000188
147/178 st92185b - serial peripheral interface (spi) serial peripheral interface (contd) the data on the sda line is sampled on the low to high transition of the scl line. spi working with an i 2 c-bus to use the spi with the i 2 c-bus protocol, the sck line is used as scl; the sdi and sdo lines, exter- nally wire-ored, are used as sda. all output pins must be configured as open drain (see figure 4 ). table 2. illustrates the typical i 2 c-bus sequence, comprising 5 phases: initialization, start, trans- mission, acknowledge and stop. it should be not- ed that only the first 8 bits are handled by the spi peripheral; the acknowledge bit must be man- aged by software, by polling or forcing the scl and sdo lines via the corresponding i/o port bits. during the transmission phase, the following i 2 c- bus features are also supported by hardware. clock synchronization in a multimaster i 2 c-bus system, when several masters generate their own clock, synchronization is required. the first master which releases the scl line stops internal counting, restarting only when the scl line goes high (released by all the other masters). in this manner, devices using dif- ferent clock sources and different frequencies can be interfaced. arbitration lost when several masters are sending data on the sda line, the following takes place: if the transmit- ter sends a 1 and the sda line is forced low by another device, the arb flag (spicr.5) is set and the sdo buffer is disabled (arb is reset and the sdo buffer is enabled when spidr is written to again). when bms is set, the peripheral clock is supplied through the int2 line by the external clock line (scl). due to potential noise spikes (which must last longer than one intclk period to be detected), rx or tx may gain a clock pulse. referring to figure 6 , if device st9-1 detects a noise spike and therefore gains a clock pulse, it will stop its transmission early and hold the clock line low, causing device st9-2 to freeze on the 7th bit. to exit and recover from this condition, the bms bit must be reset; this will cause the spi logic to be reset, thus aborting the current transmission. an end of transmission interrupt is generated fol- lowing this reset sequence. figure 91. spi arbitration n n internal serial clock bhs 0 1 st9-1 sck mspi logic control int 2 mspi control logic 0 1 bhs sck internal serial clock st9-2 int 2 1234567 st9-2-sck st9-1-sck 8 7 6 5 3 2 1 4 spike vr001410
148/178 st92185b - serial peripheral interface (spi) serial peripheral interface (contd) 7.6.7 s-bus interface the s-bus is a three-wire bidirectional data-bus, possessing functional features similar to the i 2 c- bus. as opposed to the i 2 c-bus, the start/stop conditions are determined by encoding the infor- mation on 3 wires rather than on 2, as shown in figure 8 . the additional line is referred as sen. spi working with s-bus the s-bus protocol uses the same pin configura- tion as the i 2 c-bus for generating the scl and sda lines. the additional sen line is managed through a standard st9 i/o port line, under soft- ware control (see figure 4 ). figure 92. mixed s-bus and i 2 c-bus system n figure 93. s-bus configuration n 12 3 4 56 start stop va00440 scl sda sen
149/178 st92185b - serial peripheral interface (spi) serial peripheral interface (contd) 7.6.8 im-bus interface the im-bus features a bidirectional data line and a clock line; in addition, it requires an ident line to distinguish an address byte from a data byte ( fig- ure 10 ). unlike the i 2 c-bus protocol, the im-bus protocol sends the least significant bit first; this re- quires a software routine which reverses the bit or- der before sending, and after receiving, a data byte. figure 9 shows the connections between an im-bus peripheral and an st9 spi. the sdo and sdi pins are connected to the bidirectional data pin of the peripheral device. the sdo alternate function is configured as open-drain (external 2.5k w pull-up resistors are required). with this type of configuration, data is sent to the peripheral by writing the data byte to the spidr register. to receive data from the peripheral, the user should write ffh to the spidr register, in or- der to generate the shift clock pulses. as the sdo line is set to the open-drain configuration, the in- coming data bits that are set to 1 do not affect the sdo/sdi line status (which defaults to a high level due to the ffh value in the transmit register), while incoming bits that are set to 0 pull the input line low. in software it is necessary to initialise the st9 spi by setting both cpol and cpha to 1. by using a general purpose i/o as the ident line, and forcing it to a logical 0 when writing to the spidr regis- ter, an address is sent (or read). then, by setting this bit to 1 and writing to spidr, data is sent to the peripheral. when all the address and data pairs are sent, it is necessary to drive the ident line low and high to create a short pulse. this will generate the stop condition. figure 94. st9 and im-bus peripheral n figure 95. im bus timing v dd sck sdi sdo st9 mcu im-bus clock data ident im-bus slave device protocol portx vr001427 2.5 k 2x 1 2 3 45 6 clock line data line 1 2 4 3 5 6 msb vr000172 msb lsb lsb ident
150/178 st92185b - serial peripheral interface (spi) serial peripheral interface (contd) 7.6.9 register description it is possible to have up to 3 independent spis in the same device (refer to the device block dia- gram). in this case they are named spi0 thru spi2. if the device has one spi converter it uses the register adresses of spi0. the register map is the following: note: in the register description on the following pages, register and page numbers are given using the example of spi0. spi data register (spidr) r253 - read/write register page: 0 reset value: undefined bit 7:0 = d[0:7] : spi data . this register contains the data transmitted and re- ceived by the spi. data is transmitted bit 7 first, and incoming data is received into bit 0. transmis- sion is started by writing to this register. note: spidr state remains undefined until the end of transmission of the first byte. spi control register (spicr) r254 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = spen : serial peripheral enable . 0: sck and sdo are kept tristate. 1: both alternate functions sck and sdo are ena- bled. note: furthermore, spen (together with the bms bit) affects the selection of the source for interrupt channel b0. transmission starts when data is writ- ten to the spidr register. bit 6 = bms : s-bus/i 2 c-bus mode selector . 0: perform a re-initialisation of the spi logic, thus allowing recovery procedures after a rx/tx fail- ure. 1: enable s-bus/i 2 c-bus arbitration, clock synchro- nization and start/ stop detection (spi used in an s-bus/i 2 c-bus protocol). note: when the bms bit is reset, it affects (togeth- er with the spen bit) the selection of the source for interrupt channel b0. bit 5 = arb : arbitration flag bit. this bit is set by hardware and can be reset by software. 0: s-bus/i 2 c-bus stop condition is detected. 1: arbitration lost by the spi in s-bus/i 2 c-bus mode. note: when arb is set automatically, the sdo pin is set to a high value until a write instruction on spidr is performed. bit 4 = busy : spi busy flag . this bit is set by hardware. it allows the user to monitor the spi status by polling its value. 0: no transmission in progress. 1: transmission in progress. bit 3 = cpol : transmission clock polarity . cpol controls the normal or steady state value of the clock when data is not being transferred. please refer to the following table and to figure 11 to see this bit action (together with the cpha bit). note: as the sck line is held in a high impedance state when the spi is disabled (spen = 0), the sck pin must be connected to v ss or to v cc through a resistor, depending on the cpol state. polarity should be set during the initialisation rou- tine, in accordance with the setting of all peripher- als, and should not be changed during program execution. register spin page spidr r253 spi0 0 spicr r254 spi0 0 spidr1 r253 spi1 7 spicr1 r254 spi1 7 spidr2 r245 spi2 7 spicr2 r246 spi2 7 70 d7 d6 d5 d4 d3 d2 d1 d0 70 spen bms arb busy cpol cpha spr1 spr0
151/178 st92185b - serial peripheral interface (spi) serial peripheral interface (contd) bit 2 = cpha : transmission clock phase. cpha controls the relationship between the data on the sdi and sdo pins, and the clock signal on the sck pin. the cpha bit selects the clock edge used to capture data. it has its greatest impact on the first bit transmitted (msb), because it does (or does not) allow a clock transition before the first data capture edge. figure 11 shows the relation- ship between cpha, cpol and sck, and indi- cates active clock edges and strobe times. bit 1:0 = spr[1:0]: spi rate. these two bits select one (of four) baud rates, to be used as sck. figure 96. spi data and clock timing cpol cpha sck (in figure 11 ) 0 0 1 1 0 1 0 1 (a) (b) (c) (d) spr1 spr0 clock divider sck frequency (@ intclk = 24mhz) 0 0 1 1 0 1 0 1 8 16 128 256 3000khz 1500khz 187.5khz 93.75khz (t = 0.33 m s) (t = 0.67 m s) (t = 5.33 m s) (t = 10.66 m s)
152/178 st92185b - a/d converter (a/d) 7.7 a/d converter (a/d) 7.7.1 introduction the 8 bit analog to digital converter uses a fully differential analog configuration for the best noise immunity and precision performance. the analog voltage references of the converter are connected to the internal av dd & av ss analog supply pins of the chip if they are available, otherwise to the ordi- nary v dd and v ss supply pins of the chip. the guaranteed accuracy depends on the device (see electrical characteristics). a fast sample/hold al- lows quick signal sampling for minimum warping effect and conversion error. 7.7.2 main features n 8-bit resolution a/d converter n single conversion time (including sampling time): C 138 internal system clock periods in slow mode (~5.6 s @25mhz internal system clock); C 78 intclk periods in fast mode (~6.5 s @ 12mhz internal system clock) n sample/hold: tsample= C 84 intclk periods in slow mode (~3.4 s @25mhz internal system clock) C 48 intclk periods in fast mode (~4 s @12mhz internal system clock) n up to 4 analog inputs (the number of inputs is device dependent, see device pinout) n single/continuous conversion mode n external/internal source trigger (alternate synchronization) n power down mode (zero power consumption) n 1 control logic register n 1 data register 7.7.3 general description depending on the device, up to 8 analog inputs can be selected by software. different conversion modes are provided: single, continuous, or triggered. the continuous mode performs a continuous conversion flow of the se- lected channel, while in the single mode the se- lected channel is converted once and then the log- ic waits for a new hardware or software restart. a data register (addtr) is available, mapped in page 62, allowing data storage (in single or contin- uous mode). the start conversion event can be managed by software, writing the start/stop bit of the con- trol logic register or by hardware using either: C an external signal on the extrg triggered input (negative edge sensitive) connected as an alter- nate function to an i/o port bit C an on chip event generated by another periph- eral, such as the mft (multifunction timer). figure 97. a/d converter block diagram n st9 bus successive approximation register analog mux data register control logic s/h ain1 ainx intrg (on chip event) ain0 extrg
153/178 st92185b - a/d converter (a/d) a/d converter ( contd ) the conversion technique used is successive ap- proximation, with ac coupled analog fully differen- tial comparators blocks plus a sample and hold logic and a reference generator. the internal reference (dac) is based on the use of a binary-ratioed capacitor array. this technique allows the specified monotonicity (using the same ratioed capacitors as sampling capacitor). a pow- er down programmable bit sets the a/d converter analog section to a zero consumption idle status. 7.7.3.1 operating modes the two main operating modes, single and contin- uous, can be selected by writing 0 (reset value) or 1 into the cont bit of the control logic register. single mode in single mode (cont=0 in adclr) the str bit is forced to '0' after the end of channel i-th conver- sion; then the a/d waits for a new start event. this mode is useful when a set of signals must be sam- pled at a fixed frequency imposed by a timer unit or an external generator (through the alternate synchronization feature). a simple software rou- tine monitoring the str bit can be used to save the current value before a new conversion ends (so to create a signal samples table within the in- ternal memory or the register file). furthermore, if the r242.0 bit (register ad-int, bit 0) is set, at the end of conversion a negative edge on the con- nected external interrupt channel (see interrupts chapter) is generated to allow the reading of the converted data by means of an interrupt routine. continuous mode in continuous mode (cont=1 in adclr) a con- tinuous conversion flow is entered by a start event on the selected channel until the str bit is reset by software. at the end of each conversion, the data register (adcdr) content is updated with the last conver- sion result, while the former value is lost. when the conversion flow is stopped, an interrupt request is generated with the same modality previously de- scribed. 7.7.3.2 alternate synchronization this feature is available in both single/continuous modes. the negative edge of external extrg sig- nal or the occurrence of an on-chip event generat- ed by another peripheral can be used to synchro- nize the conversion start with a trigger pulse. these events can be enabled or masked by pro- gramming the trg bit in the adclr register. the effect of alternate synchronization is to set the str bit, which is cleared by hardware at the end of each conversion in single mode. in continuous mode any trigger pulse following the first one will be ignored. the synchronization source must pro- vide a pulse (1.5 internal system clock, 125ns @ 12 mhz internal clock) of minimum width, and a period greater (in single mode) than the conver- sion time (~6.5us @ 12 mhz internal clock). if a trigger occurs when the str bit is still '1' (conver- sions still in progress), it is ignored (see electrical characteristics). warning: if the extrg or intrg signals are al- ready active when trg bit is set, the conversion starts immediately. 7.7.3.3 power-up operations before enabling any a/d operation mode, set the pow bit of the adclr register at least 60 s be- fore the first conversion starts to enable the bias- ing circuits inside the analog section of the con- verter. clearing the pow bit is useful when the a/d is not used so reducing the total chip power consumption. this state is also the reset configu- ration and it is forced by hardware when the core is in halt state (after a halt instruction execution). 7.7.3.4 register mapping it is possible to have two independent a/d convert- ers in the same device. in this case they are named a/d 0 and a/d 1. if the device has one a/d converter it uses the register addresses of a/d 0. the register map is the following: if two a/d converters are present, the registers are renamed, adding the suffix 0 to the a/d 0 registers and 1 to the a/d 1 registers. register address adn page 62 (3eh) f0h a/d 0 addtr0 f1h a/d 0 adclr0 f2h a/d 0 adint0 f3-f7h a/d 0 reserved f8h a/d 1 addtr1 f9h a/d 1 adclr1 fah a/d 1 adint1 fb-ffh a/d 1 reserved
154/178 st92185b - a/d converter (a/d) a/d converter ( contd ) 7.7.4 register description a/d control logic register (adclr) r241 - read/write register page: 62 reset value: 0000 0000 (00h) this 8-bit register manages the a/d logic opera- tions. any write operation to it will cause the cur- rent conversion to be aborted and the logic to be re-initialized to the starting configuration. bit 7:5 = c[2:0] : channel address. these bits are set and cleared by software. they select channel i conversion as follows: bit 4 = fs : fast/slow . this bit is set and cleared by software. 0: fast mode. single conversion time: 78 x intclk (5.75s at intclk = 12 mhz) 1: slow mode. single conversion time: 138 x intclk (11.5s at intclk = 12 mhz) note : fast conversion mode is only allowed for in- ternal speeds which do not exceed 12 mhz. bit 3 = trg : external/internal trigger enable . this bit is set and cleared by software. 0: external/internal trigger disabled. 1: either a negative (falling) edge on the extrg pin or an on chip event writes a 1 into the str bit, enabling start of conversion. note: triggering by on chip event is available on devices with the multifunction timer (mft) periph- eral. bit 2 = pow : power enable . this bit is set and cleared by software. 0: disables all power consuming logic. 1: enables the a/d logic and analog circuitry. bit 1 = cont : continuous/single mode select . this bit it set and cleared by software. 0: single mode: after the current conversion ends, the str bit is reset by hardware and the con- verter logic is put in a wait status. to start anoth- er conversion, the str bit has to be set by soft- ware or hardware. 1: select continuous mode, a continuous flow of a/d conversions on the selected channel, start- ing when the str bit is set. bit 0 = str : start/stop . this bit is set and cleared by software. it is also set by hardware when the a/d is synchronized with an external/internal trigger. 0: stop conversion on channel i. an interrupt is generated if the str was previously set and the ad-int bit is set. 1: start conversion on channel i warning: when accessing this register, it is rec- ommended to keep the related a/d interrupt chan- nel masked or disabled to avoid spurious interrupt requests. 70 c2 c1 c0 fs trg pow cont str c2 c1 c0 channel enabled 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 channel 0 channel 1 channel 2 channel 4 channel 3
155/178 st92185b - a/d converter (a/d) a/d converter ( contd ) a/d channel i data register (addtr) r240 - read/write register page: 62 reset value: undefined the result of the conversion of the selected chan- nel is stored in the 8-bit addtr, which is reloaded with a new value every time a conversion ends. bit 7:0 = r[7:0] : channel i conversion result . a/d interrupt register (adint) register page: 62 r242 - read/write reset value: 0000 0001 (01h) bit 7:1 = reserved. bit 0 = ad-int : ad converter interrupt enable . this bit is set and cleared by software. it allows the interrupt source to be switched between the a/d converter and an external interrupt pin (see inter- rupts chapter). 0: a/d interrupt disabled. external pin selected as interrupt source. 1: a/d interrupt enabled 70 r.7 r.6 r.5 r.4 r.3 r.2 r.1 r.0 70 0 0 0 0 0 0 0 ad-int
156/178 st92185b - voltage synthesis tuning converter (vs) 7.8 voltage synthesis tuning converter (vs) 7.8.1 description the on-chip voltage synthesis (vs) converter al- lows the generation of a tuning reference voltage in a tv set application. the peripheral is com- posed of a 14-bit counter that allows the conver- sion of the digital content in a tuning voltage, avail- able at the vs output pin, by using pwm (pulse width modulation) and brm (bit rate modulation) techniques. the 14-bit counter gives 16384 steps which allow a resolution of approximately 2 mv over a tuning voltage of 32 v. this corresponds to a tuning resolution of about 40 khz per step in uhf band (the actual value will depend on the characteristics of the tuner). the tuning word consists of a 14-bit word con- tained in the registers vsdr1 (r254) and vsdr2 (r255) both located in page 59. coarse tuning (pwm) is performed using the sev- en most significant bits. fine tuning (brm) is per- formed using the the seven least significant bits. with all 0s loaded, the output is 0. as the tuning voltage increases from all 0s, the number of puls- es in one period increases to 128 with all pulses being the same width. for values larger than 128, the pwm takes over and the number of pulses in one period remains constant at 128, but the width changes. at the other end of the scale, when al- most all 1s are loaded, the pulses will start to link together and the number of pulses will decrease. when all 1s are loaded, the output will be almost 100% high but will have a low pulse (1/16384 of the high pulse). 7.8.2 output waveforms included inside the vs are the register latches, a reference counter, pwm and brm control circuit- ry. the clock for the 14-bit reference counter is de- rived from the main system clock (referred to as intclk) after a division by 4. for example, using an internal 12 mhz on-chip clock (see timing & clock controller chapter) leads to a 3 mhz input for the vs counter. from the point of view of the circuit, the seven most significant bits control the coarse tuning, while the seven least significant bits control the fine tuning. from the application and software point of view, the 14 bits can be considered as one binary number. as already mentioned the coarse tuning consists of a pwm signal with 128 steps: we can consider the fine tuning to cover 128 coarse tuning cycles. the vs tuning converter is implemented with 2 separate outputs (vso1 and vso2) that can drive 2 separate alternate function outputs of 2 stand- ard i/o port bits. a control bit allows you to choose which output is activated (only one output can be activated at a time). when a vs output is not selected because the vs is disabled or because the second output is select- ed, it stays at a logical one level, allowing you to use the corresponding i/o port bit either as a nor- mal i/o port bit or for a possible second alternate function output. a second control bit allows the vs function to be started (or stopped) by software.
157/178 st92185b - voltage synthesis tuning converter (vs) voltage synthesis (contd) pwm generation the counter increments continuously, clocked at intclk divided by 4. whenever the 7 least signif- icant bits of the counter overflow, the vs output is set. the state of the pwm counter is continuously compared to the value programmed in the 7 most significant bits of the tuning word. when a match occurs, the output is reset thus generating the pwm output signal on the vs pin. this pulse width modulated signal must be fil- tered, using an external rc network placed as close as possible to the associated pin. this pro- vides an analog voltage proportional to the aver- age charge passed to the external capacitor. thus for a higher mark/space ratio (high time much greater than low time) the average output voltage is higher. the external components of the rc net- work should be selected for the filtering level re- quired for control of the system variable. figure 98. typical pwm output filter figure 99. pwm generation c ext output voltage r ext pwm out 1k counter 127 7-bit pwm value overflow overflow overflow 000 t pwm output t intclk/4 x 128
158/178 st92185b - voltage synthesis tuning converter (vs) voltage synthesis (contd) figure 100. pwm simplified voltage output after filtering (2 examples) v dd 0v 0v dd v v ripple (mv) v outavg "charge" "discharge" "charge" "discharge" 0v v v 0v outavg v (mv) ripple v vr01956 "charge" "discharge" "charge" "discharge" pwmout dd dd pwmout output voltage output voltage
159/178 st92185b - voltage synthesis tuning converter (vs) voltage synthesis (contd) brm generation the brm bits allow the addition of a pulse to wid- en a standard pwm pulse for specific pwm cy- cles. this has the effect of fine-tuning the pwm duty cycle (without modifying the base duty cycle), thus, with the external filtering, providing additional fine voltage steps. the incremental pulses (with duration of t intclk / 4) are added to the beginning of the original pwm pulse and thus cause the pwm high time to be ex- tended by this time with a corresponding reduction in the low time. the pwm intervals which are add- ed to are specified in the lower 7 bits of the tuning word and are encoded as shown in the following table. table 29. 7-bit brm pulse addition positions the brm values shown may be combined togeth- er to provide a summation of the incremental pulse intervals specified. the pulse increment corresponds to the pwm res- olution. figure 101. simplified filtered voltage output schematic with brm added fine tuning no. of pulses added at the following cycles 0000001 64 0000010 32, 96 0000100 16, 48, 80, 112 0001000 8, 24,... 104, 120 0010000 4, 12,... 116, 124 0100000 2, 6,... 122, 126 1000000 1, 3,... 125, 127 v dd pwmout 0v v dd output voltage 0v brm = 1 brm = 0 t intclk /4 brm extended pulse == =
160/178 st92185b - voltage synthesis tuning converter (vs) voltage synthesis (contd) 7.8.3 register description vs data and control register 1 (vsdr1) r254 - read/write register page: 59 reset value: 0000 0000 (00h) bit 7 = vse : vs enable bit. 0: vs tuning converter disabled (i.e. the clock is not forwarded to the vs counter and the 2 out- puts are set to 1 (idle state) 1: vs tuning converter enabled. bit 6 = vswp : vs output select this bit controls which vs output is enabled to out- put the vs signal. 0: vso1 output selected 1: vso2 output selected bit 5:0 = vd[13:8] tuning word bits. these bits are the 6 most significant bits of the tuning word forming the pwm selection. the vd13 bit is the msb. vs data and control register 2 (vsdr2) r255 - read/write register page: 59 reset value: 0000 0000 (00h) bit 7:0 = vd[7:0] tuning word bits. these bits are the 8 least significant data bits of the vs tuning word. all bits are accessible. bits vd6 - vd0 form the brm pulse selection. vd7 is the lsb of the 7 bits forming the pwm selection. 76543210 vse vswp vd13 vd12 vd11 vd10 vd9 vd8 70 vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0
161/178 st92185b - pwm generator 7.9 pwm generator 7.9.1 introduction the pwm (pulse width modulated) signal genera- tor allows the digital generation of up to 8 analog outputs when used with an external filtering net- work. the unit is based around an 8-bit counter which is driven by a programmable 4-bit prescaler, with an input clock signal equal to the internal clock intclk divided by 2. for example, with a 12 mhz internal clock, using the full 8-bit resolution, a fre- quency range from 1465 hz up to 23437 hz can be achieved. higher frequencies, with lower resolution, can be achieved by using the autoclear register. as an ex- ample, with a 12 mhz internal clock, a maximum pwm repetition rate of 93750 hz can be reached with 6-bit resolution. note: the number of output pins is device de- pendant. refer to the device pinout description. figure 102. pwm block diagram. autoclear compare 7 compare 6 compare 5 compare 4 compare 3 compare 2 compare 1 compare 0 vr01765 pwm7 pwm0 8 bit counter 4 bit presc. control logic intclk/2 output logic st9 register bus
162/178 st92185b - pwm generator pwm generator (contd) up to 8 pwm outputs can be selected as alternate functions of an i/o port. each output bit is inde- pendently controlled by a separate compare reg- ister. when the value programmed into the com- pare register and the counter value are equal, the corresponding output bit is set. the output bit is re- set by a counter clear (by overflow or autoclear), generating the variable pwm signal. each output bit can also be complemented or dis- abled under software control. 7.9.2 register mapping the st9 can have one or two pwm generators. each has 13 registers mapped in page 59 (pwm0) or page 58 (pwm1). in the register description on the following pages, the register page refers to pwm0 only. figure 103. pwm action when compare register = 0 (no complement) figure 104. pwm action when compare register = 3 (no complement) register address register function r240 cm0 ch. 0 compare register r241 cm1 ch. 1 compare register r242 cm2 ch. 2 compare register r243 cm3 ch. 3 compare register r244 cm4 ch. 4 compare register r245 cm5 ch. 5 compare register r246 cm6 ch. 6 compare register r247 cm7 ch. 7 compare register r248 acr autoclear register r249 crr counter read register r250 pctlr prescaler/ reload reg. r251 ocplr output complement reg. r252 oer output enable register r253- r255 reserved vr0a1814 pwm clock pwm output counter=autoclear value counter=0 counter=1 vr001814 pwm clock pwm output counter=autoclear value counter=0 counter=3
163/178 st92185b - pwm generator pwm generator (contd) 7.9.2.1 register description compare register 0 (cm0) r240 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 0. when the programmed content is equal to the counter content, a set operation is performed on pwm output 0 (if the output has not been com- plemented or disabled). bit 7:0 = cm0.[7:0] : pwm compare value chan- nel 0. compare register 1 (cm1) r241 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 1. compare register 2 (cm2) r242 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 2. compare register 3 (cm3) r243 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 3. compare register 4 (cm4) r244 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 4. compare register 5 (cm5) r245 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 5. compare register 6 (cm6) r246 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 6. compare register 7 (cm7) r247 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 7. 70 cm0.7 cm0.6 cm0.5 cm0.4 cm0.3 cm0.2 cm0.1 cm0.0 70 cm1.7 cm1.6 cm1.5 cm1.4 cm1.3 cm1.2 cm1.1 cm1.0 70 cm2.7 cm2.6 cm2.5 cm2.4 cm2.3 cm2.2 cm2.1 cm2.0 70 cm3.7 cm3.6 cm3.5 cm3.4 cm3.3 cm3.2 cm3.1 cm3.0 70 cm4.7 cm4.6 cm4.5 cm4.4 cm4.3 cm4.2 cm4.1 cm4.0 70 cm5.7 cm5.6 cm5.5 cm5.4 cm5.3 cm5.2 cm5.1 cm5.0 70 cm6.7 cm6.6 cm6.5 cm6.4 cm6.3 cm6.2 cm6.1 cm6.0 70 cm7.7 cm7.6 cm7.5 cm7.4 cm7.3 cm7.2 cm7.1 cm7.0
164/178 st92185b - pwm generator pwm generator (contd) autoclear register (acr) r248 - read/write register page: 59 reset value: 1111 1111 (ffh) this register behaves exactly as a 9th compare register, but its effect is to clear the crr counter register, so causing the desired pwm repetition rate. the reset condition generates the free running mode. so, ffh means count by 256. bit 7:0 = ac[7:0] : autoclear count value. when 00 is written to the compare register, if the acr register = ffh, the pwm output bit is always set except for the last clock count (255 set and 1 reset; the converse when the output is comple- mented). if the acr content is less than ffh, the pwm output bit is set for a number of clock counts equal to that content (see figure 2). writing the compare register constant equal to the acr register value causes the output bit to be al- ways reset (or set if complemented). example: if 03h is written to the compare regis- ter, the output bit is reset when the crr counter reaches the acr register value and set when it reaches the compare register value (after 4 clock counts, see figure 3). the action will be reversed if the output is complemented. the pwm mark/ space ratio will remain constant until changed by software writing a new value in the acr register. counter register (crr) r249 - read only register page: 59 reset value: 0000 0000 (00h) this read-only register returns the current counter value when read. the 8 bit counter is initialized to 00h at reset, and is a free running up counter. bit 7:0 = cr[7:0] : current counter value. prescaler and control register (pctl) r250 - read/write register page: 59 reset value: 0000 1100 (0ch) bit 7:4 = pr[3:0] pwm prescaler value . these bits hold the prescaler preset value. this is reloaded into the 4-bit prescaler whenever the prescaler (down counter) reaches the value 0, so determining the 8-bit counter count frequency. the value 0 corresponds to the maximum counter frequency which is intclk/2. the value fh corre- sponds to the maximum frequency divided by 16 (intclk/32). the reset condition initializes the prescaler to the maximum counter frequency. bit 3:2 = reserved. forced by hardware to 1 bit 1 = clr : counter clear. this bit when set, allows both to clear the counter, and to reload the prescaler. the effect is also to clear the pwm output. it returns 0 if read. bit 0 = ce : counter enable. this bit enables the counter and the prescaler when set to 1. it stops both when reset without affecting their current value, allowing the count to be suspended and then restarted by software on fly. 70 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 70 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 70 pr3 pr2 pr1 pr0 1 1 clr ce pr[3:0] divider factor frequency 0 1 intclk/2 (max.) 1 2 intclk/4 2 3 intclk/6 .. .. .. fh 16 intclk/32 (min.)
165/178 st92185b - pwm generator pwm generator (contd) output complement register (ocpl) r251- read/write register page 59 reset value: 0000 0000 (00h) this register allows the pwm output level to be complemented on an individual bit basis. in default mode (reset configuration), each com- parison true between a compare register and the counter has the effect of setting the corresponding output. at counter clear (either by autoclear comparison true, software clear or overflow when in free run- ning mode), all the outputs are cleared. by setting each individual bit (ocpl.x) in this reg- ister, the logic value of the corresponding output will be inverted (i.e. reset on comparison true and set on counter clear). example: when set to 1, the ocpl.1 bit comple- ments the pwm output 1. bit 7 = ocpl.7 : complement pwm output 7. bit 6 = ocpl.6 : complement pwm output 6. bit 5 = ocpl.5 : complement pwm output 5. bit 4 = ocpl.4 : complement pwm output 4. bit 3 = ocpl.3 : complement pwm output 3. bit 2 = ocpl.2 : complement pwm output 2. bit 1 = ocpl.1 : complement pwm output 1. bit 0 = ocpl.0 : complement pwm output 0. output enable register (oer) r252 - read/write register page: 59 reset value: 0000 0000 (00h) these bits are set and cleared by software. 0: force the corresponding pwm output to logic level 1. this allows the port pins to be used for normal i/o functions or other alternate functions (if available). 1: enable the corresponding pwm output. example: writing 03h into the oe register will en- able only pwm outputs 0 and 1, while outputs 2, 3, 4, 5, 6 and 7 will be forced to logic level 1. bit 7 = oe.7 : output enable pwm output 7. bit 6 = oe.6 : output enable pwm output 6. bit 5 = oe.5 : output enable pwm output 5. bit 4 = oe.4 : output enable pwm output 4. bit 3 = oe.3 : output enable pwm output 3. bit 2 = oe.2 : output enable pwm output 2. bit 1 = oe.1 : output enable pwm output 1. bit 0 = oe.0 : output enable pwm output 0. 70 ocpl.7 ocpl.6ocpl.5 ocpl.4ocpl.3 ocpl.2 ocpl.1ocpl.0 70 oe.7 oe.6 oe.5 oe.4 oe.3 oe.2 oe.1 oe.0
166/178 st92185b - electrical characteristics 8 electrical characteristics absolute maximum ratings note : stress above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating onl y and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended perio ds may affect device reliability. recommended operating conditions symbol parameter value unit v dd supply voltage v ss - 0.3 to v ss + 6.5 v v ssa analog ground v ss - 0.3 to v ss + 0.3 v v dda analog supply voltage v dd -0.3 to v dd +0.3 v v i input voltage v ss - 0.3 to v dd +0.3 v v ai analog input voltage (a/d converter) v ss - 0.3 to v dd +0.3 v ssa - 0.3 to v dda +0.3 v v o output voltage v ss - 0.3 to v dd + 0.3 v t stg storage temperature - 55 to + 150 c i inj pin injected current maximum accumulated pin injected current in device - 5 to + 5 - 50 to +5 0 ma ma symbol parameter value unit min. max. t a operating temperature 0 70 c v dd supply voltage 4.5 5.5 v v dda analog supply voltage (pll) 4.5 5.5 v f osce external oscillator frequency 3.3 8.7 mhz f osci internal clock frequency (intclk) 24 mhz
167/178 st92185b - electrical characteristics dc electrical characteristics ( v dd = 5v +/-10%; t a = 0 to 70c; unless otherwise specified) symbol parameter test conditions value unit min. max. v ihck clock in high level external clock 0.7 v dd v v ilck clock in low level external clock 0.3 v dd v v ih input high level ttl 2.0 v v il input low level ttl 0.8 v v ih input high level cmos 0.8 v dd v v il input low level cmos 0.2 v dd v v ihrs reset in high level 0.7 v dd v v ilrs reset in low level 0.3 v dd v v hyrs reset in hysteresis 0.3 v v ihy p2.(1:0) input hysteresis 0.9 v v ihvh hsync/vsync input high level 0.7 v dd v v ilvh hsync/vsync input low level 0.3 v dd v v hyhv hsync/vsync input hysteresis 0.5 v v oh output high level push-pull ild=-0.8ma v dd -0.8 v v ol output low level push-pull ld=+1.6ma 0.4 v i wpu weak pull-up current bidir. state v ol = 3v v ol = 7v 50 350 a i lkio i/o pin input leakage current 0 168/178 st92185b - electrical characteristics ac electrical characteristics pin capacitance ( v dd = 5v +/-10%; t a = 0 to 70c; unless otherwise specified)) current consumption ( v dd = 5v +/-10%; t a = 0 to 70c; unless otherwise specified) notes : 1. port 0 is configured in push-pull output mode (output is high). ports 2, 3, 4 and 5 are configured in bi-directional weak pull- up mode resistor. the external clock pin (oscin) is driven by a square wave external clock at 8 mhz. the internal clock prescaler is in divide-by -1 mode. 2. the cpu is fed by a 24 mhz frequency issued by the main clock controller. vsync is tied to v ss , hsync is driven by a 15625hz clock. all peripherals working including display. 3. the cpu is fed by a 24 mhz frequency issued by the main clock controller. vsync is tied to v ss , hsync is driven by a 15625hz clock. the tdsram interface and the slicers are working; the display controller is not working. 4. vsync and hsync tied to v ss . external clock pin (oscin) is hold low. all peripherals are disabled. external interrupt timing table (rising or falling edge mode) ( v dd = 5v +/-10%; t a = 0 to 70c; unless otherwise specified)) tpc is the intclk clock period. symbol parameter conditions value unit min max c io pin capacitance digital input/output 10 pf symbol parameter conditions value unit min typ. max i dd1 run mode current notes 1,2; all on 70 100 ma i dda1 run mode analog current (pin v dda ) timing controller on 35 50 ma i dd2 halt mode current notes 1,4 10 100 a i dda2 halt mode analog current (pin v dda ) notes 1,4 40 100 a symbol parameter conditions value unit intclk=24 mhz. min max t wlr low level pulse width tpc+12 95 ns t whr high level pulse width tpc+12 95 ns
169/178 st92185b - electrical characteristics ac electrical characteristics (contd) spi timing table ( v dd = 5v +/-10%; t a = 0 to 70c; cload= 50pf) (1) tpc is the oscin clock period; tpmc is the main clock frequency period. skew corrector timing table ( v dd = 5v +/-10%, t a = 0 to 70c, unless otherwise specified) (*) the osd jitter is measured from leading edge to leading edge of a single character row on consecutive tv lines. the value i s an envelope of 100 fields symbol parameter condition value unit min max t sdi input data set-up time tbd ns t hdi input data hold time (1) oscin/2 as internal clock 1intclk +100ns ns t dov sck to output data valid tbd ns t hdo output data hold time tbd ns t wskl sck low pulse width tbd ns t wskh sck high pulse width tbd ns symbol parameter conditions max value unit t jskw jitter on rgb output 36 mhz skew corrector clock frequency 5* ns
170/178 st92185b - electrical characteristics ac electrical characteristics (contd) osd dac characteristics (rom devices only) ( v dd = 5v +/-10%, t a = 0 to 70c, unless otherwise specified). osd dac characteristics (eprom and otp devices only) ( v dd = 5v +/-10%, t a = 0 to 70c, unless otherwise specified). symbol parameter conditions value unit min typical max output impedance: fb,r,g,b 300 500 700 ohm output voltage: fb,r,g,b cload= 20pf rl = 100k code= 111 1.000 1.250 v code= 011 0.450 0.500 v code= 000 0.025 0.080 v fb= 1 2.4 2.7 3.4 v fb= 0 0 0.025 0.080 v global voltage accuracy +/-5 % symbol parameter conditions value unit min typical max output impedance: fb,r,g,b 300 500 700 ohm output voltage: fb,r,g,b cload= 20pf rl = 100k code= 111 1.100 1.400 v code= 011 0.600 0.800 v code= 000 0.200 0.350 v fb= 1 v dd -0.8 v fb= 0 0.400 v global voltage accuracy +/-5 %
171/178 st92185b - electrical characteristics ac electrical characteristics (contd) a/d converter, external trigger timing table ( v dd = 5v +/-10%; t a = 0 to 70c; unless otherwise specified a/d converter. analog parameters table ( v dd = 5v +/-10%; t a = 0 to 70c; unless otherwise specified)) notes: (*) the values are expected at 25 celsius degrees with v dd = 5v (**) 'lsbs' , as used here, as a value of v dd /256 (1) @ 24 mhz external clock (2) including sample time (3) it must be considered as the on-chip series resistance before the sampling capacitor (4) dnl error= max {[v(i) -v(i-1)] / lsb-1} inl error= max {[v(i) -v(0)] / lsb-i} absolute accuracy= overall max conversion error symbol parameter oscin divide by 2;min/max oscin divide by 1; min/max value unit min max t low pulse width 1.5 intclk ns t high pulse distance ns t ext period/fast mode 78+1 intclk s t str start conversion delay 0.5 1.5 intclk core clock issued by timing controller t low pulse width ns t high pulse distance ns t ext period/fast mode s t str start conversion delay ns parameter value unit note typ (*) min max (**) analog input range v ss v dd v conversion time fast/slow 78/138 intclk (1,2) sample time fast/slow 51.5/87.5 intclk (1) power-up time 60 s resolution 8 bits differential non linearity 3 5 lsbs (4) integral non linearity 4 5 lsbs (4) absolute accuracy 2 3 lsbs (4) input resistance 1.5 kohm (3) hold capacitance 1.92 pf
172/178 st92185b - general information 9 general information 9.1 package mechanical data figure 105. 56-pin shrink plastic dual in line package, 600-mil width figure 106. 42-pin shrink plastic dual in-line package, 600-mil width dim. mm inches min typ max min typ max a 6.35 0.250 a1 0.38 0.015 a2 3.18 4.95 0.125 0.195 b 0.41 0.016 b2 0.89 0.035 c 0.20 0.38 0.008 0.015 d 50.29 53.21 1.980 2.095 e 15.01 0.591 e1 12.32 14.73 0.485 0.580 e 1.78 0.070 ea 15.24 0.600 eb 17.78 0.700 l 2.92 5.08 0.115 0.200 number of pins n56 pdip56s dim. mm inches min typ max min typ max a 5.08 0.200 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.46 0.56 0.018 0.022 b2 1.02 1.14 0.040 0.045 c 0.23 0.25 0.38 0.009 0.010 0.015 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.600 0.630 e1 12.70 13.72 14.48 0.500 0.540 0.570 e 1.78 0.070 ea 15.24 0.600 eb 18.54 0.730 ec 0.00 1.52 0.000 0.060 l 2.54 3.30 3.56 0.100 0.130 0.140 number of pins n42 pdip42s
173/178 st92185b - general information package mechanical data (contd) figure 107. 64-pin thin quad flat package figure 108. 56-pin shrink ceramic dual in line package, 600-mil width dim mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 d3 12.00 0.472 e 16.00 0.630 e1 14.00 0.551 e3 12.00 0.472 e 0.80 0.031 k 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 nd 16 ne 16 l1 l k dim. mm inches min typ max min typ max a 4.17 0.164 a1 0.76 0.030 b 0.38 0.46 0.56 0.015 0.018 0.022 b1 0.76 0.89 1.02 0.030 0.035 0.040 c 0.23 0.25 0.38 0.009 0.010 0.015 d 50.04 50.80 51.56 1.970 2.000 2.030 d1 48.01 1.890 e1 14.48 14.99 15.49 0.570 0.590 0.610 e 1.78 0.070 g 14.12 14.38 14.63 0.556 0.566 0.576 g1 18.69 18.95 19.20 0.736 0.746 0.756 g2 1.14 0.045 g3 11.05 11.30 11.56 0.435 0.445 0.455 g4 15.11 15.37 15.62 0.595 0.605 0.615 l 2.92 5.08 0.115 0.200 s 1.40 0.055 number of pins n56 cdip56sw
174/178 st92185b - general information figure 109. 42-pin shrink ceramic dual in-line package, 600-mil width figure 110. 64-pin ceramic quad flat package dim. mm inches min typ max min typ max a 4.01 0.158 a1 0.76 0.030 b 0.38 0.46 0.56 0.015 0.018 0.022 b1 0.76 0.89 1.02 0.030 0.035 0.040 c 0.23 0.25 0.38 0.009 0.010 0.015 d 36.68 37.34 38.00 1.444 1.470 1.496 d1 35.56 1.400 e1 14.48 14.99 15.49 0.570 0.590 0.610 e 1.78 0.070 g 14.12 14.38 14.63 0.556 0.566 0.576 g1 18.69 18.95 19.20 0.736 0.746 0.756 g2 1.14 0.045 g3 11.05 11.30 11.56 0.435 0.445 0.455 g4 15.11 15.37 15.62 0.595 0.605 0.615 l 2.92 5.08 0.115 0.200 s 0.89 0.035 number of pins n42 cdip42sw dim mm inches min typ max min typ max a 3.27 0.129 a1 0.50 0.020 b 0.30 0.35 0.45 0.012 0.014 0.018 c 0.13 0.15 0.23 0.005 0.006 0.009 d 16.65 17.20 17.75 0.656 0.677 0.699 d1 13.57 13.97 14.37 0.534 0.550 0.566 d3 12.00 0.472 e 0.80 0.031 g 12.70 0.500 g2 0.96 0.038 l 0.35 0.80 0.014 0.031 0 8.31 0.327 number of pins n64 cqfp064w
175/178 st92185b - general information 9.2 ordering information each device is available for production in a user programmable version (otp) as well as in factory coded version (rom). otp devices are shipped to customer with a default blank content ffh, while rom factory coded parts contain the code sent by customer. the common eprom versions for de- bugging and prototyping features the maximum memory size and peripherals of the family. care must be taken to only use resources available on the target device. 9.2.1 transfer of customer code customer code is made up of the rom contents and the list of the selected options (if any). the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file gener- ated by the development tool. all unused bytes must be set to ffh. figure 111. rom factory coded device types device package temp. range xxx / code name (defined by stmicroelectronics) 1= standard 0 to +70 c bn= plastic sdip56 bj= plastic sdip42 t= plastic tqfp64 st92185b1 st92185b2 st92185b3
176/178 st92185b - general information stmicroelectronics option list st92185b customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom code* : . . . . . . . . . . . . . . . . . . *the rom code name assigned by st. stmicroelectronics reference: device: [ ] st92185b1b1 [ ] st92185b2b1 [ ] st92185b3b1 package : [ ] sdip42 [ ] sdip56 [ ] tqfp64 temperature range : 0 to 70 c software development: [ ] stmicroelectronics [ ] customer [ ] external laboratory special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _" for marking, one line is possible with maximum 14 characters. authorized characters are let- ters, digits, '.', '-', '/' and spaces only. please consult your local st microelectronics sales office for other marking details if required. notes : osd code : [ ] osd file filename [........ .osd] quantity forecast : [..................] k units per year for a period of : [..................] years preferred production start dates : [../../..] (yy/mm/dd) date customer signature :
177/178 st92185b - revision history 10 revision history rev. main changes date 1.0 first release on dms 01/11/00 1.1 16k rom added / tqfp64 added p1, changed device summary; added one feature (pin-compatible with...) and changed one feature (pin-compatible eprom, etc.). added option list. 03/15/00 1.2 added section 10 on page 177 . updated figure 3 on page 10 and figure 5 on page 12 . changed non-linearity values in a/d converter analog parameters table. modified table 9 on page 59 . modified section 4.2 on page 57 . 11 oct 2001 1.3 modification of the absolute maximum rating of the supply voltage value in section 8 on page 166 . 16 jan 2002
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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